IP Library Granted Patent US 11,164,780
Granted Patent B2
US 11,164,780 · App. 16/435,121 · Granted Nov 2, 2021

Process integration approach for selective metal via fill

Inventors: Shi You (Sunnyvale, CA); He Ren (San Jose, CA); Mehul Naik (San Jose, CA); Yi Xu (San Jose, CA); Feng Chen (San Jose, CA)
Assignee: APPLIED MATERIALS, INC.
H01L21/76877H01L21/02063H01L21/02068H01L21/31144H01L21/76814H01L21/76846H01L21/76847H01L21/76849
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Quick Facts
Patent No.
US 11,164,780
App. No.
16/435,121
Granted
Nov 2, 2021
Kind
B2
Abstract

Methods and apparatus for an interconnect formed on a substrate and a method of forming the interconnect thereon. In embodiments, the methods include etching through a hard mask disposed atop a low-k dielectric layer to form a via through the low-k dielectric layer and expose a conductive surface; contacting the conductive surface with dilute hydrofluoric acid to remove contaminants therefrom; removing the hard mask disposed atop the low-k dielectric layer; and applying a remote hydrogen plasma to the conductive surface to form an exposed portion of the conductive surface.

Claims (41)

1. A method of forming an interconnect, comprising:

etching through a hard mask disposed atop a low-k dielectric layer to form a via through the low-k dielectric layer and expose a conductive surface;

contacting the conductive surface with dilute hydrofluoric acid to remove contaminants therefrom;

subsequently, removing the hard mask disposed atop the low-k dielectric layer;

subsequent to removing the hard mask, applying a remote hydrogen plasma to the exposed portion of the conductive surface to clean the exposed portion of the conductive surface;

depositing a first metal of a first type in the via;

forming a trench in communication with the via;

depositing a barrier layer within the trench and atop the exposed portion of the conductive surface;

depositing a liner layer atop the barrier layer; and

filling the trench with a second metal different than the first metal of a first type.

2. The method of claim 1 , wherein contacting the conductive surface with dilute hydrofluoric acid to remove contaminants therefrom is performed before removing the hard mask disposed atop the low-k dielectric layer.

3. The method of claim 1 , wherein removing the hard mask disposed atop the low-k dielectric layer is performed before applying a remote hydrogen plasma to the conductive surface to form an exposed portion of the conductive surface.

4. The method of claim 1 , wherein the dilute hydrofluoric acid is a 100 to 1000:1 dHF solution.

5. The method of claim 1 , wherein the first metal of a first type is one of ruthenium, tungsten, cobalt, aluminum, or combinations thereof.

6. The method of claim 1 , further comprising adding a capping layer atop the second metal.

7. A method of forming an interconnect, comprising:

forming a via and a trench in a film stack comprising a hard mask and a dielectric layer disposed on a substrate to expose a conductive surface;

contacting the conductive surface with dilute hydrofluoric acid;

removing the hard mask;

applying a remote plasma to the exposed conductive surface to clean the exposed portion of the conductive surface;

depositing a first metal of a first type in the via;

depositing a barrier layer upon the first metal and exposed surfaces of the trench;

depositing a liner layer upon the barrier layer; and

filling the trench with a second metal different than the first metal.

8. The method of claim 7 , wherein contacting the conductive surface with dilute hydrofluoric acid occurs prior to removing the hard mask.

9. The method of claim 7 , wherein contacting the conductive surface with dilute hydrofluoric acid occurs prior to removing the hard mask, and wherein removing the hard mask occurs prior to applying a remote plasma to the conductive surface to form an exposed portion of the conductive surface.

10. The method of claim 7 , wherein the first metal of a first type is one of ruthenium, tungsten, cobalt, aluminum, or combinations thereof.

11. The method of claim 7 , wherein the barrier layer comprises TiN or TaN.

12. The method of claim 7 , wherein the liner layer corn cobalt.

13. The method of claim 7 , wherein the second metal is copper.

14. The method of claim 7 , wherein a capping layer is disposed atop the second metal.

15. A non-transitory computer readable medium having instructions stored thereon that, when executed, cause a method a method of forming an interconnect, comprising:

etching through a hard mask disposed atop a low-k dielectric layer to form a via through the low-k dielectric layer and expose a conductive surface;

contacting the conductive surface with dilute hydrofluoric acid to remove contaminants therefrom;

subsequently, removing the hard mask disposed atop the o k dielectric layer;

subsequent to removing the hard mask, applying a remote hydrogen plasma to the exposed portion of the conductive surface to clean the exposed portion of the conductive surface;

depositing a first metal of a first type in the via;

forming a trench in communication with the via;

depositing a barrier layer within the trench and atop the exposed portion of the conductive surface;

depositing a liner layer atop the barrier layer; and

filling the trench with a second metal different than the first metal of a first type.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 14, 2019
From: YOU, SHI; REN, HE; NAIK, MEHUL; XU, YI; CHEN, FENG
To: APPLIED MATERIALS, INC.
Reel/Frame 049473/0469 →
Continuity (1)
Related Publication 20200388533A1 · Dec 10, 2020
Cited By (1)
US 12,444,682