IP Library › Granted Patent US 11,164,784
Granted Patent B2
US 11,164,784 · App. 16/548,666 · Granted Nov 2, 2021

Open-drain transistor monitoring circuit in a multi-chip package to control power

Inventors: Jonathan S. Parry (Boise, ID); Stephen L. Miller (Boise, ID); Liang Yu (Boise, ID)
Assignee: MICRON TECHNOLOGY, INC.
H01L21/82H01L24/06H01L24/49H01L24/92H01L25/0657H01L25/50
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Quick Facts
Patent No.
US 11,164,784
App. No.
16/548,666
Granted
Nov 2, 2021
Kind
B2
Abstract

A technique to provide power management for multiple dice. The technique provides for determining for each respective die of the multiple dice, power consumption for operating each respective die; and generating a respective signal from each respective die that corresponds to the power consumption of each respective die. The technique further provides, for each respective signal, driving a respective open-drain transistor to conduct, in which an output of each open-drain transistor connects to the common node and the common node connects to a reference voltage, to change a voltage of a common node corresponding to the respective signal; and utilizing the voltage of the common node to indicate total power consumption of the dice.

Claims (33)

1. A method comprising:

determining for each respective die of a plurality of dice, power consumption for operating each respective die;

generating a respective signal from each respective die that corresponds to the power consumption of each respective die;

for each respective signal, driving a respective open-drain transistor to conduct, an output of each open-drain transistor coupled to a common node, the common node coupled to a reference voltage, wherein driving one or more of the open-drain transistors to conduct changes a voltage of the common node corresponding to the respective signals; and

utilizing a cumulative change of the voltage of the common node from the reference voltage to indicate total power consumption of the plurality of dice.

2. The method of claim 1 , further comprising comparing the voltage of the common node to a threshold level for power consumption set for the plurality of dice.

3. The method of claim 2 , wherein the threshold level is peak power consumption for the plurality of dice.

4. The method of claim 2 , further comprising, for at least one die, performing a power consuming operation in response to determining that the voltage of the common node does not exceed the threshold level.

5. The method of claim 1 , wherein the reference voltage is a power supply voltage for the plurality of dice.

6. The method of claim 1 , wherein each respective signal drives a respective plurality of open-drain transistors.

7. The method of claim 6 , wherein each respective signal drives the open-drain transistors into saturation when conducting.

8. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, are capable of causing the processing device to perform operations comprising:

determining for each respective die of a plurality of dice, power consumption for operating each respective die;

generating a respective signal from each respective die that corresponds to the power consumption of each respective die;

for each respective signal, driving a respective open-drain transistor to conduct, an output of each open-drain transistor coupled to a common node, the common node coupled to a reference voltage, wherein driving one or more of the open-drain transistors to conduct changes a voltage of the common node corresponding to the respective signals; and

utilizing a cumulative change of the voltage of the common node from the reference voltage to indicate total power consumption of the plurality of dice.

9. The non-transitory computer-readable storage medium of claim 8 , wherein the instructions are capable of further causing the processing device to perform operations comprising comparing the voltage of the common node to a threshold level for power consumption set for the plurality of dice.

10. The non-transitory computer-readable storage medium of claim 9 , wherein the threshold level is peak power consumption for the plurality of dice.

11. The non-transitory computer-readable storage medium of claim 9 , wherein the instructions are capable of further causing the processing device to perform operations comprising, for at least one die, performing a power consuming operation in response to determining that the voltage of the common node does not exceed the threshold level.

12. The non-transitory computer-readable storage medium of claim 8 , wherein the reference voltage is a power supply voltage for the plurality of dice.

13. A system comprising:

a plurality of dice, in which each die of the plurality of dice contains one or more non-volatile memory components, wherein each die includes a power management logic to:

determine power consumption for operating each respective die;

generate a respective signal that corresponds to the power consumption of the die; and

drive a respective open-drain transistor to conduct to change a voltage of a common node corresponding to the respective signal; and

a pull-up resistor to couple the common node to a reference voltage, wherein the voltage of the common node indicates total power consumption of the plurality of dice.

14. The system of claim 13 , wherein the plurality of dice compare the voltage of the common node to a threshold level for power consumption set for the plurality of dice.

15. The system of claim 14 , wherein the threshold level is peak power consumption for the plurality of dice.

16. The system of claim 14 , wherein at least one die performs a power consuming operation in response to determining that the voltage of the common node does not exceed the threshold level.

17. The system of claim 13 , wherein the reference voltage is a power supply voltage for the plurality of dice.

18. The system of claim 13 , wherein each respective signal drives a respective plurality of open-drain transistors.

19. The system of claim 18 , wherein each respective signal drives the open-drain transistors into saturation when conducting.

20. The system of claim 13 , wherein each power management logic adjusts the respective signal for supply voltage and temperature fluctuations.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 22, 2019
From: PARRY, JONATHAN S.; MILLER, STEPHEN L.; YU, LIANG
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050140/0671 →
Continuity (1)
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