Electrostatic discharge protection circuit and electronic device thereof
An electrostatic discharge protection circuit and a semiconductor device are provided. The circuit includes: a power source terminal, a ground terminal, and a discharge path. The discharge path includes a clamp transistor and a MOS transistor connected in series and integrated into a same semiconductor substrate with different types. For the MOS transistor, a gate electrode is electrically connected to a substrate terminal; a first electrode is one of a source electrode and a drain electrode; a second electrode is another one of the source electrode and the drain electrode; the first electrode is electrically connected to a gate electrode of the clamp transistor; and the second electrode is electrically connected to the ground terminal. When an electrostatic discharge occurs, the MOS transistor is turned on to form parasitic current between a substrate terminal of the clamp transistor and the second electrode of the MOS transistor.
1. An electrostatic discharge protection circuit, comprising a power source terminal, a ground terminal, and a discharge path, wherein:
the discharge path includes a clamp transistor and a MOS transistor connected in series;
the clamp transistor and the MOS transistor are integrated into a same semiconductor substrate, and have different types;
for the MOS transistor, a gate electrode is electrically connected to a substrate terminal;
for the MOS transistor, a first electrode is one of a source electrode and a drain electrode, and a second electrode is another one of the source electrode and the drain electrode;
for the MOS transistor, the first electrode is electrically connected to a gate electrode of the clamp transistor, and the second electrode is electrically connected to the ground terminal; and
when an electrostatic discharge occurs, the MOS transistor is turned on to form parasitic current between a substrate terminal of the clamp transistor and the second electrode of the MOS transistor.
2. The circuit according to claim 1 , wherein:
the clamp transistor is a PMOS transistor and the MOS transistor is an NMOS transistor.
3. The circuit according to claim 2 , further including a first capacitor and a first resistor, wherein:
a first terminal of the first capacitor is electrically connected to the power source terminal;
a first terminal of the first resistor is electrically connected to a second terminal of the first capacitor, and a second terminal of the first resistor is electrically connected to the ground terminal;
a second terminal of the first capacitor is electrically connected to the substrate terminal of the MOS transistor; and
when the electrostatic discharge occurs, the first resistor and the first capacitor trigger the substrate terminal of the MOS transistor to have a high voltage, to turn on the MOS transistor.
4. The circuit according to claim 3 , further including a diode, wherein:
a first terminal of the diode is electrically connected to the substrate terminal, and a second terminal of the diode is electrically connected to the ground terminal.
5. The circuit according to claim 3 , wherein:
the first resistor is one of a non-silicide poly resistor, a gate soft tie high NMOS resistor, a gate soft tie low PMOS resistor, a metal parasitic resistor, or a high-resistance resistor.
6. The circuit according to claim 2 , further including a second resistor, a second capacitor, and one or more inverters connected in series, wherein:
a first terminal of the second resistor is electrically connected to the power source terminal;
a first terminal of the second capacitor is electrically connected to a second terminal of the second resistor, and a second terminal of the second capacitor is electrically connected to the ground terminal;
an input terminal of a first inverter among the one or more inverters is electrically connected between the second resistor and the second capacitor, and an output terminal of a last inverter among the one or more inverters is electrically connected to the substrate terminal of the MOS transistor;
when the electrostatic discharge occurs, the second resistor, the second capacitor, and the one or more inverters trigger the substrate terminal of the MOS transistor to have a high voltage, to turn on the MOS transistor; and
a number of the one or more inverters is singular.
7. The circuit according to claim 6 , wherein each inverter of the one or more inverters includes a P-type transistor and an N-type transistor, wherein:
a gate electrode of the P-type transistor is electrically connected to a gate electrode of the N-type transistor;
a source electrode of the P-type transistor is electrically connected to the power source terminal;
a source electrode of the N-type transistor is electrically connected to the ground terminal;
a drain electrode of the N-type transistor is electrically connected to a drain electrode of the P-type transistor;
a first terminal of the inverter is located between the gate electrode of the P-type transistor and the gate electrode of the N-type transistor; and
a second terminal of the inverter is located between the drain electrode of the P-type transistor and the drain electrode of the N-type transistor.
8. The circuit according to claim 6 , further including a diode, wherein:
a first terminal of the diode is electrically connected between a second terminal of the last inverter among the one or more inverters and the substrate terminal of the MOS transistor; and
a second terminal of the diode is electrically connected to the ground terminal.
9. The circuit according to claim 1 , wherein:
the electrostatic discharge protection circuit protects a fin field-effect transistor (FinFET).
10. The circuit according to claim 1 , wherein:
a gate structure of the clamp transistor and a gate structure of the MOS transistor are disposed on a surface of the semiconductor substrate alternately.
11. An electronic device, including an electrostatic discharge protection circuit and a semiconductor device to be protected, wherein:
the electrostatic discharge protection circuit includes a power source terminal, a ground terminal, and a discharge path, wherein:
the discharge path includes a clamp transistor and a MOS transistor connected in series;
the clamp transistor and the MOS transistor are integrated into a same semiconductor substrate, and have different types;
for the MOS transistor, a gate electrode is electrically connected to a substrate terminal;
for the MOS transistor, a first electrode is one of a source electrode and a drain electrode, and a second electrode is another one of the source electrode and the drain electrode;
for the MOS transistor, the first electrode is electrically connected to a gate electrode of the clamp transistor, and the second electrode is electrically connected to the ground terminal; and
when an electrostatic discharge occurs, the MOS transistor is turned on to form parasitic current between a substrate terminal of the clamp transistor and the second electrode of the MOS transistor;
and
a first terminal of the semiconductor device to be protected is electrically connected to the power source terminal, and a second terminal of the semiconductor device to be protected is electrically connected to the ground terminal.