Semiconductor structure and method for manufacturing the same
The present disclosure provides a semiconductor structure and a method for manufacturing a semiconductor structure. The semiconductor structure includes a substrate, a transistor on the substrate, and an isolation structure. The transistor includes an epitaxial region on the substrate, having a first side boundary and a second side boundary opposite to the first side boundary, wherein the first side boundary of the epitaxial region is conformal to a sidewall of the isolation structure.
1. A semiconductor structure, comprising:
a substrate;
a transistor on the substrate, the transistor comprising:
an epitaxial region on the substrate, having a first side boundary and a second side boundary opposite to the first side boundary;
an isolation structure on the substrate, the first side boundary of the epitaxial region being conformal to a sidewall of the isolation structure, wherein a bottom surface of the isolation structure is lower than a bottom surface of the epitaxial region, and a top surface of the isolation structure is higher than a top surface of the epitaxial region;
a fin structure on the substrate adjacent to the isolation structure; and
a dielectric layer between the fin structure and the isolation structure, wherein the dielectric layer is contacting both the fin structure and the isolation structure.
2. The semiconductor structure of claim 1 , wherein a channel of the transistor comprises a fin or a plurality of nanowires.
3. The semiconductor structure of claim 1 , wherein the dielectric layer comprises a plurality of different materials.
4. The semiconductor structure of claim 3 , wherein a thickness of each of the plurality of materials is in a range of 1 to 3.5 nanometers.
5. The semiconductor structure of claim 1 , wherein a thickness of the dielectric layer is in a range of 1 to 3.5 nanometers.
6. The semiconductor structure of claim 1 , further comprising:
an inner spacer on the dielectric layer and between a channel of the transistor and the isolation structure.
7. The semiconductor structure as claimed in claim 1 , wherein the transistor further comprises:
a gate structure across the fin structure; and
a gate spacer layer on a sidewall of the gate structure.
8. A semiconductor structure, comprising:
a substrate;
a plurality of fin structures extending along a first direction over the substrate;
a plurality of low-k isolation strips extending along the first direction over the substrate and disposed alternately between the plurality of fin structures;
a plurality of high-k isolation segments disposed on the plurality of low-k isolation strips; and
a plurality of gate structures surrounding the plurality of low-k isolation strips and the plurality of high-k isolation segments.
9. The semiconductor structure of claim 8 , wherein a top surface of the plurality of high-k isolation segments is coplanar with a top surface of the plurality of gate structures.
10. The semiconductor structure of claim 8 , wherein the plurality of gate structures are separated by the plurality of low-k isolation strips and the plurality of high-k isolation segments.
11. The semiconductor structure of claim 8 , further comprising:
a plurality of inner spacers between one of the plurality of fin structures and an adjacent one of the plurality of low-k isolation strips.
12. The semiconductor structure of claim 8 , further comprising a plurality of nanowires over each of the plurality of fin structures.
13. The semiconductor structure of claim 8 , wherein one or more dielectric materials are between the plurality of fin structure and an adjacent one of the plurality of low-k isolation strip.
14. The semiconductor structure of claim 8 , wherein a first fin of the plurality of fin structures is between a first low-k isolation strip and a second low-k isolation strip of the plurality of low-k isolation strips, and a first distance between the first fin and the first low-k isolation strip is less than a second distance between the first fin and the second low-k isolation strip.
15. A semiconductor structure, comprising:
a substrate fin;
a plurality of nanowires stacked over the substrate fin; a first low-k isolation strip adjacent to the substrate fin and the plurality of nanowires; and
an inner spacer interposing an upper portion of the first low-k isolation strip and the plurality of nanowires and interposing adjacent two of the nanowires.
16. The semiconductor structure of claim 15 , further comprising:
a first dielectric layer interposing a lower portion of the first low-k isolation strip and the substrate fin and below the first low-k isolation strip.
17. The semiconductor structure of claim 16 , wherein the inner spacer is located over and in contact with the first dielectric layer.
18. The semiconductor structure of claim 15 , further comprising:
a high-k isolation segment covering an upper surface of the first low-k isolation strip and an upper surface of the inner spacer.
19. The semiconductor structure of claim 15 , further comprising:
a second low-k isolation strip adjacent to the substrate fin and the plurality of nanowires; and
a second dielectric layer interposing a lower portion of the second low-k isolation strip and the substrate fin and below the second low-k isolation strip, wherein a width of the first dielectric layer is less than a width of the second dielectric layer.
20. The semiconductor structure of claim 19 , further comprising:
a gate spacer layer over the second dielectric layer and interposing an upper portion of the second low-k isolation strip and the plurality of nanowires.