Stacked upper fin and lower fin transistor with separate gate
Forming a first opening in a first double stacked fin and forming a second opening in a second double stacked fin, by removing a high silicon germanium layer, forming a low k spacer, removing a dummy gate, and removing portions of the low k spacer from an outer surface of the first double stacked fin, and an outer surface of the second double stacked fin. A structure including an upper fin of a double stacked fin separated from a lower fin of a double stacked fin by a low k spacer and by a p type field effect transistor work function metal layer (PFET WFM), where a horizontal lower surface of the upper fin is coplanar with a horizontal upper surface of the low k spacer and a horizontal lower surface of the low k spacer is coplanar with a horizontal upper surface of the PFET WFM.
1. A semiconductor structure comprising:
an upper fin of a double stacked fin separated from a lower fin of the double stacked fin by a low k spacer and by a p type field effect transistor work function metal layer, wherein a horizontal lower surface of the upper fin is coplanar with a horizontal upper surface of the low k spacer and a horizontal lower surface of the low k spacer is coplanar with a first horizontal upper surface of the p type field effect transistor work function metal layer, and
an inner level dielectric layer, wherein a horizontal lower surface of the inner level dielectric layer is coplanar with a portion of an upper surface of the p type field effect transistor work function metal layer, a vertical side surface of the inner level dielectric layer is coplanar with a vertical side surface of the p-type field effect transistor work function metal layer, and a horizontal upper surface of the inner level dielectric layer is coplanar with a horizontal lower surface of an n type field effect transistor work function metal layer.
2. The semiconductor structure according to claim 1 , further comprising:
a dielectric layer, wherein a horizontal lower surface of the dielectric layer is coplanar with a second horizontal upper surface of the p type field effect transistor work function metal layer, and a vertical side surface of the dielectric layer is coplanar with a vertical side surface of the low k spacer.
3. The semiconductor structure according to claim 2 , further comprising:
the n type field effect transistor work function metal layer, wherein a lower surface of the n type field effect transistor work function metal layer is coplanar with an upper surface of the dielectric layer, and a vertical side surface of the n type field effect transistor work function metal layer is coplanar with a portion of the vertical side surface of the low k spacer.
4. The semiconductor structure according to claim 1 , wherein the p type field effect transistor work function metal layer surrounds the upper fin of the double stacked fin, and the n type field effect transistor work function metal layer surrounds the lower fin of the double stacked fin.
5. The semiconductor structure according to claim 1 , wherein
a dielectric layer, wherein a horizontal lower surface of the dielectric layer is coplanar with a second horizontal upper surface of the p type field effect transistor work function metal layer, and a vertical side surface of the dielectric layer is coplanar with a vertical side surface of the low k spacer; and
a portion of the vertical side surface of the inner level dielectric is coplanar with a portion of the vertical side surface of the dielectric layer.
6. The semiconductor structure according to claim 1 , further comprising:
a p-type field effect transistor work function metal layer contact; and
a n-type field effect transistor work function metal layer contact.