Vertical intercalation device for neuromorphic computing
A semiconductor device with an array of vertically stacked electrochemical random-access memory (ECRAM) devices, includes holes formed in a vertical stack of horizontal electrodes. The horizontal electrodes are horizontally aligned and stacked vertically at different vertical levels within the vertical stack and separated by first fill layers. The semiconductor device includes a stack deposition, including a channel layer, and an electrolyte layer, formed over the vertical stack and holes. Selector layers fill holes. The selector layers include an inner selector layer and outer selector layers. The channel layer, the electrolyte layer and outer selector layers are recessed to the inner selector layer and a fill layer is deposited over the vertical stack. The fill layer has been reduced down to the top of the inner selector layer.
1. A method for fabricating an array of vertically stacked electrochemical random-access memory (ECRAM) devices, comprising:
forming at least one hole in a vertical stack of horizontal electrodes, wherein the horizontal electrodes are horizontally aligned and stacked vertically at different vertical levels within the vertical stack and separated by first fill layers;
forming a stack deposition including a channel layer, and an electrolyte layer over the vertical stack and at least one hole;
depositing selector layers to fill the at least one hole, wherein the selector layers include an inner selector layer and outer selector layers;
recessing the channel layer, the electrolyte layer and outer selector layers to the inner selector layer;
depositing an additional fill layer over the vertical stack; and
reducing the additional fill layer down to the top of the inner selector layer.
2. The method of claim 1 , wherein the selector layers are configured to allow programming of individual ECRAM device without cross-talk.
3. The method of claim 1 , wherein a structure of the array of vertically stacked ECRAM devices incorporates a three-terminal electrochemical memory.
4. The method of claim 1 , a structure of the array of vertically stacked ECRAM devices encapsulates the electrolyte layer.
5. The method of claim 1 , wherein forming at least one hole in a vertical stack of horizontal electrodes further comprises:
etch drilling the at least one hole on the vertical stack of horizontal electrodes with patterning.
6. The method of claim 1 , further comprising:
forming the vertical stack of horizontal electrodes via multiple deposition horizontal electrode layers, and barrier layers on the first fill layers and a substrate.
7. The method of claim 1 , wherein depositing the selector layers to fill the at least one hole further comprises:
performing chemical mechanical planarization stopping on a barrier layer of the vertical stack.
8. The method of claim 1 , wherein the electrolyte layer includes Lithium Phosphorous Oxynitride (LiPON), the channel layer includes tungsten oxide (WO 3 ) and the selector layers include at least one of titanium nitride (TiN) and tungsten (W), silicon oxynitride (SiO x N y ) and at least one of copper (Cu) and silver (Ag).
9. The method of claim 1 , wherein the electrolyte layer includes at least one of Hafnium oxide (HfO 2 ) and Cerium oxide (CeO), and the selector layers include at least one of titanium nitride (TiN) and tungsten (W), silicon oxynitride (SiO x N y ) and at least one of copper (Cu) and silver (Ag).
10. The method of claim 1 , wherein depositing the selector layers further comprises:
depositing a diffusive memristor to be used as a selector.
11. A semiconductor device including an array of vertically stacked electrochemical random-access memory (ECRAM) devices, comprising:
at least one hole formed in a vertical stack of horizontal electrodes, wherein the horizontal electrodes are horizontally aligned and stacked vertically at different vertical levels within the vertical stack and separated by first fill layers;
a stack deposition, including a channel layer, and an electrolyte layer, formed over the vertical stack and at least one hole;
selector layers filling the at least one hole, wherein the selector layers include an inner selector layer and outer selector layers, wherein the channel layer, the electrolyte layer and outer selector layers are recessed to the inner selector layer; and
an additional fill layer deposited over the vertical stack, wherein the fill layer is reduced down to the top of the inner selector layer.
12. The semiconductor device of claim 11 , wherein the selector layers are configured to allow programming of individual ECRAM device without cross-talk.
13. The semiconductor device of claim 11 , wherein a structure of the array of vertically stacked ECRAM devices incorporates a three-terminal electrochemical memory.
14. The semiconductor device of claim 11 , wherein a structure of the array of vertically stacked ECRAM devices encapsulates the electrolyte layer.
15. The semiconductor device of claim 11 , wherein the electrolyte layer includes Lithium Phosphorous Oxynitride (LiPON), the channel layer includes tungsten oxide (WO 3 ) and the selector layers include at least one of titanium nitride (TiN) and tungsten (W), silicon oxynitride (SiO x N y ) and at least one of copper (Cu) and silver (Ag).
16. The semiconductor device of claim 11 , wherein the electrolyte layer includes at least one of Hafnium oxide (HfO 2 ) and Cerium oxide (CeO), and the selector layers include at least one of titanium nitride (TiN) and tungsten (W), silicon oxynitride (SiO x N y ) and at least one of copper (Cu) and silver (Ag).
17. The semiconductor device of claim 11 , wherein the selector layers further comprise a diffusive memristor to be used as a selector.
18. A semiconductor device including an array of vertically stacked electrochemical random-access memory (ECRAM) devices, comprising:
at least one hole formed in a vertical stack of horizontal electrodes, wherein the horizontal electrodes are horizontally aligned and stacked vertically at different vertical levels within the vertical stack and separated by first fill layers;
a stack deposition, including a channel layer, and an electrolyte layer, formed over the vertical stack and the at least one hole, wherein the channel layer includes tungsten oxide (WO 3 ) and the electrolyte layer includes Lithium Phosphorous Oxynitride (LiPON);
selector layers filling the at least one hole, wherein the selector layers include an inner selector layer and outer selector layers, wherein the channel layer, the electrolyte layer and outer selector layers are recessed to the inner selector layer and the inner selector layer includes at least one of copper (Cu) and silver (Ag); and
an additional fill layer deposited over the vertical stack, wherein the fill layer is reduced down to the top of the inner selector layer.
19. The semiconductor device of claim 18 , wherein a structure of the array of vertically stacked ECRAM devices incorporates a three-terminal electrochemical memory.
20. The semiconductor device of claim 18 , wherein a structure of the array of vertically stacked ECRAM devices encapsulates the electrolyte layer.