Semiconductor device and production method
The present invention provides a Group III nitride semiconductor device in which current concentration at the corners of the trench is suppressed. The semiconductor device has a pattern in which regular hexagonal unit cells are arranged in a honeycomb pattern. The semiconductor layer is sectionalized into regular hexagonal patterns by the trench. The recess has a small regular hexagonal pattern contained in the regular hexagonal pattern of the semiconductor layer sectionalized by the trench, which is obtained by reducing the regular hexagon of the semiconductor layer with the same center. Moreover, the regular hexagonal pattern of the recess is rotated by 30° with respect to the regular hexagon of the semiconductor layer. The Mg activation ratio is lower in the vicinity of corners of the trench than that in other regions in the vicinity of side walls of the trench of the p-type layer.
1. A semiconductor device comprising:
a Group III nitride semiconductor layer including a first n-type layer, a p-type layer formed on the first n-type layer, and a second n-type layer formed on the p-type layer;
a trench having a depth reaching from surface of the second n-type layer to the first n-type layer, and sectionalizing the Group III nitride semiconductor layer into a plurality of unit cells to have a predetermined planar pattern; and
a recess having a depth reaching from the surface of the second n-type layer to the p-type layer,
wherein a planar pattern of the recess is a regular polygon contained in an unit cell the planar pattern of the Group III nitride semiconductor layer, a side of the regular polygon is not parallel to a side of the planar pattern of the Group III nitride semiconductor layer, a>b when a shortest distance from a corner of the trench to the recess is defined as a and a shortest distance from a side of the trench to the recess is defined as b in a plan view, and
an Mg activation ratio in the p-type layer is lower in a vicinity of the corner of the trench than an Mg activation ratio in other regions, in a vicinity of a side wall of the trench.
2. The semiconductor device according to claim 1 ,
wherein the trench comprises a planar pattern in which a plurality of regular hexagons of the planar pattern of the Group III nitride semiconductor layer are arranged in a honeycomb pattern, and
the recess has a planar pattern of regular hexagon obtained by reducing the regular hexagon of the planar pattern of the Group III nitride semiconductor layer with a same center, and rotated with respect to the regular hexagon of the planar pattern of the Group III nitride semiconductor layer.
3. The semiconductor device according to claim 2 , wherein the planar pattern of the recess is rotated by 25° to 35° with respect to the regular hexagon of the planar pattern of the Group III nitride semiconductor layer.
4. The semiconductor device according to claim 3 , wherein the side wall of the trench is an a-plane, and the side wall of the recess is a m-plane.
5. The semiconductor device according to claim 3 , wherein a-b is 0.8 μm to 1.9 μm.
6. The semiconductor device according to claim 2 , wherein a diameter of an inscribed circle of the regular hexagon of the planar pattern of the recess is 0.8 μm to 2.0 μm.
7. The semiconductor device according to claim 2 , wherein the side wall of the trench is an a-plane, and the side wall of the recess is a m-plane.
8. The semiconductor device according to claim 2 , wherein a b is 0.8 μm to 1.9 μm.
9. The semiconductor device according to claim 1 , wherein the side wall of the trench is an a-plane, and the side wall of the recess is a m-plane.
10. The semiconductor device according to claim 1 , wherein a b is 0.8 μm to 1.9 μm.
11. The semiconductor device according to claim 1 , wherein the semiconductor device is a vertical trench gate type field effect transistor.