Reverse computational fuzzy extractor and method for authentication

1. A method of authenticating a first device, the method comprising:

measuring a first response bit string of a physical unclonable function of the first device with respect to a challenge bit string, the physical unclonable function being provided by a component of the first device;

deriving, with a processor of the first device, a shared secret bit string from a uniformly distributed random vector;

encoding, with the processor of the first device, a helper bit string by multiplying a uniformly distributed random matrix with the uniformly distributed random vector and adding the first response bit string to a result of the multiplication; and

transmitting, with a transceiver of the first device, the helper bit string to a second device that is remote from the first device.

2. The method of claim 1 further comprising:

receiving, with a transceiver of the second device, the helper bit string from the first device;

reading, with a processor of the second device, a previously measured second response bit string of the physical unclonable function of the first device with respect to the challenge bit string from a memory storage of the second device, the second response bit string being measured and stored at a time of manufacture of the first device;

subtracting, with the processor of the second device, the second response bit string from the helper bit string;

decoding, with the processor of the second device, a result of the subtraction using the uniformly distributed random matrix, the shared secret bit string being provided from the decoding if the first response bit string is within a threshold level of similarity to the second response bit string, the decoding outputting an error value otherwise; and

transmitting, with the transceiver of the second device, one of (i) a confirmation message indicating that authentication was successful and (ii) a rejection message indicating that authentication was unsuccessful to the first device, the confirmation message being transmitted only if shared secret bit string was provided from the decoding, the rejection message being transmitted otherwise.

3. The method of claim 2 further comprising:

receiving, with the transceiver of the first device, the one of (i) the confirmation message and (ii) the rejection message from the second device.

4. The method of claim 1 further comprising:

receiving, with the transceiver of the first device, the challenge bit string from the second device.

5. The method of claim 1 further comprising:

reading the challenge bit string from a memory storage of the first device.

6. The method of claim 1 further comprising:

reading, with the processor of the first device, the uniformly distributed random matrix from a memory storage of the first device, the uniformly distributed random matrix being stored in the memory storage at a time of manufacture of the first device.

7. The method of claim 1 further comprising:

receiving, with the transmitter of the first device, the uniformly distributed random matrix from the second device; and

storing, with the processor of the first device, the received uniformly distributed random matrix in a memory storage of the first device, the received uniformly distributed random matrix replacing any currently stored version of the uniformly distributed random matrix in the memory storage of the first device.

8. The method of claim 1 further comprising:

transmitting, with the transmitter of the first device, an authentication request message, the authentication request message including an identifier of the first device.

9. The method of claim 1 , wherein the physical unclonable function is provided by one of the processor of the first device and a memory storage of the first device.

10. The method of claim 1 , wherein the physical unclonable function is provided by a microelectromechanical system of the first device that is configured to provide the physical unclonable function.

11. A system comprising:

a first device having (i) a transceiver, (ii) a memory storage, and (iii) a processor operably connected to the transceiver and the memory storage, a component of the first device being configured to provide a physical unclonable function that is usable by the processor, the processor configured to:

receive a measurement of a first response bit string of the physical unclonable function of the first device with respect to a challenge bit string;

derive a shared secret bit string from a uniformly distributed random vector;

encode a helper bit string by multiplying a uniformly distributed random matrix with the uniformly distributed random vector and adding the first response bit string to a result of the multiplication; and

operate the transceiver of the first device to transmit the helper bit string to a second device that is remote from the first device.

12. The system of claim 11 further comprising:

the second device having (i) a transceiver, (ii) a memory storage, and (iii) a processor operably connected to the transceiver and the memory storage, the processor configured to:

operate the transceiver of the second device to receive the helper bit string from the first device;

read a previously measured second response bit string of the physical unclonable function of the first device with respect to the challenge bit string from the memory storage of the second device, the second response bit string being measured and stored at a time of manufacture of the first device;

subtract the second response bit string from the helper bit string;

decode a result of the subtraction, the shared secret bit string being provided from the decoding if the first response bit string is within a threshold level of similarity to the second response bit string, the decoding outputting an error value otherwise; and

transmit one of (i) a confirmation message indicating that authentication was successful and (ii) a rejection message indicating that authentication was unsuccessful to the first device, the confirmation message being transmitted only if shared secret bit string was provided from the decoding, the rejection message being transmitted otherwise.

13. The system of claim 12 , the processor of the first device being further configured to:

operate the transceiver of the first device to receive the one of (i) the confirmation message and (ii) the rejection message from the second device.

14. The system of claim 11 , the processor of the first device being further configured to:

operate the transceiver of the first device to receive the challenge bit string from the second device.

15. The system of claim 11 , the processor of the first device being further configured to:

read the challenge bit string from the memory storage of the first device.

16. The system of claim 11 , the processor of the first device being further configured to:

read the uniformly distributed random matrix from the memory storage of the first device, the uniformly distributed random matrix being stored in the memory storage at a time of manufacture of the first device.

17. The system of claim 11 , the processor of the first device being further configured to:

operate the transceiver of the first device to receive the uniformly distributed random matrix from the second device; and

store the received uniformly distributed random matrix in the memory storage of the first device, the received uniformly distributed random matrix replacing any currently stored version of the uniformly distributed random matrix in the memory storage of the first device.

18. The system of claim 11 , the processor of the first device being further configured to:

operate the transceiver of the first device to transmit an authentication request message, the authentication request message including an identifier of the first device.

19. The system of claim 11 , wherein the physical unclonable function is provided by one of the processor of the first device and the memory storage of the first device.

20. The system of claim 11 , the first device further comprising:

a microelectromechanical system operably connected to the processor and configured to provide the physical unclonable function.