Systems, methods and apparatus for low latency memory integrity mac for trust domain extensions
The disclosed embodiments generally relate to methods, systems and apparatuses to authenticate instructions on a memory circuitry. In an exemplary embodiment, the disclosure relates to a computing device (e.g., a memory protection engine) to protect integrity of one or more memory circuitry. The computing device may include: a key-hash operator configured to provide a Message Authentication Code (MAC) for a secure Hash Algorithm (SHA) as a function of a hash-key, MAC-key, metadata and data; a multi-round (MR) circuitry configured to receive the MAC from the key-hash operator and to compute substantially all SHA round-functions during each clock cycle, the multi-round circuitry further comprising combination logic to process all sub-round functions of the SHA function substantially simultaneously; and a Memory Integrity Pipeline (MIP) engine to compute a hash digest, the hash digest further comprising a MAC key, a metadata and the cache line data; the MIP further comprising an input prep logic, an SHA pipeline logic and an MAC validation logic.
1. A computing device to protect integrity of one or more memory circuitry, the computing device comprising:
a key-hash operator configured to provide a Message Authentication Code (MAC) for a secure Hash Algorithm (SHA) as a function of a hash-key, MAC-key, domain-specific metadata and cache-line data;
a multi-round (MR) circuitry configured to receive the MAC from the key-hash operator and to compute substantially all SHA round-functions during each clock cycle, the multi-round circuitry further comprising combination logic to process all sub-round functions of the SHA function substantially simultaneously; and
a Memory Integrity Pipeline (MIP) engine to compute a hash digest, the hash digest further comprising a MAC key, a metadata and the cache line data; the MIP further comprising an input prep logic, an SHA pipeline logic and an MAC validation logic;
wherein the computing device including key-hash operator, MR circuitry and MIP engine are implemented on a System-on-Chip;
wherein the MAC-key includes a secret bit-string that provides authentication of the cache-line data.
2. The computing device of claim 1 , wherein the SHA comprises SHA3.
3. The computing device of claim 1 , wherein the low-latency MAC is configured to perform key-hash operation on an SHA3 hash function.
4. The computing device of claim 1 , wherein the MR circuitry is configured to receive the MAC from the key-hash operator and to compute substantially all SHA round-functions in parallel during one clock cycle.
5. The computing device of claim 1 , wherein the multi-round circuitry further comprises combination logic to process five sub-round operations substantially simultaneously.
6. The computing device of claim 1 , wherein the multi-round circuitry is configured to process 1600-bit parallel data path substantially simultaneously and during one clock cycle.
7. The computing device of claim 1 , wherein the multi-round circuitry is configured to compute at least four SHA round functions in one clock cycle.
8. The computing device of claim 1 , wherein the multi-round circuitry comprises a digital logic having at least 15.8k gates.
9. The computing device of claim 1 , wherein the hash-key is a function of Keccak 1600 algorithm, the metadata is in the range of about 0 to 320 bits and the cache-line data is 512 bits.
10. The computing device of claim 1 , wherein the MIP circuitry further comprises at least one temporary register to retain an intermediate hash result and a pipeline control circuitry.
11. The computing device of claim 10 , wherein the intermediate hash result is communicated to the MR circuitry.
12. A System on Chip (“SoC”) to protect integrity of one or more memory circuitry, the SoC comprising:
a key-hash operator configured to provide a Message Authentication Code (MAC) for a secure Hash Algorithm (SHA) as a function of a hash-key, MAC-key, domain-specific metadata and cache-line data;
a multi-round (MR) circuitry configured to receive the MAC from the key-hash operator and to compute substantially all SHA round-functions during each clock cycle, the multi-round circuitry further comprising combination logic to process all sub-round functions of the SHA function substantially simultaneously and during one clock cycle; and
a Memory Integrity Pipeline (MIP) engine to compute a hash digest, the hash digest further comprising a MAC key, a metadata and the cache line data; the MIP further comprising an input prep logic, an SHA pipeline logic and an MAC validation logic;
wherein the key-hash operator, MR circuitry and MIP engine are implemented on a unitary SoC and wherein the cache-line data is 512 bits.