Temperature effect compensation in memory arrays

1. A memory system having a temperature effect compensation mechanism, the system comprising:

a plurality of memory cells organized in an array having two or more rows of memory cells arranged horizontally and two or more columns of memory cells arranged vertically, wherein the plurality of memory cells includes a supercell structure having shared sources and erase gates and has an operating temperature range; and

a temperature-dependent biasing circuit, wherein the temperature-dependent biasing circuit is configured to:

reduce a biasing voltage to the plurality of memory cells in response to the temperature of the array being at or near an upper end of the operating temperature range; and

increase the biasing voltage to the plurality of memory cells in response to the temperature of the array being at or near a lower end of the operating temperature range.

2. The memory system of claim 1 , wherein each row of memory cells within the array has a separate temperature-dependent biasing circuit that controls the biasing voltage for each memory cell within the row.

3. The memory system of claim 2 , wherein the memory system is used for in-memory applications and inputs are applied directly to the temperature-dependent biasing circuit.

4. The memory system of claim 3 , wherein each of the two or more rows of memory cells includes a first gate and a second gate, and wherein digital inputs are applied to the first gate and inputs from the temperature-dependent biasing circuit are applied to the second gate.

5. The memory system of claim 3 , wherein each of the two or more rows of memory cells includes a first gate and a second gate, and wherein the first gate is used for row selection and the second gate is used for both digital inputs and inputs from the temperature-dependent biasing circuit.

6. The memory system of claim 1 , wherein the temperature-dependent biasing circuit controls the biasing voltage for memory cells in a plurality of rows within the array.

7. The memory system of claim 1 , wherein each row of the two or more rows of memory cells includes an extra input configured to turn on and off the memory cells during either a read or write operation.

8. The memory system of claim 7 , wherein analog or digital inputs are applied to the extra input.

9. The memory system of claim 1 , wherein the temperature-dependent biasing circuit converts an analog input current to a temperature-dependent voltage that is used to bias the memory cells within the array.

10. The memory system of claim 9 , wherein the memory cells convert the biasing voltage to a current based on an amplitude of the biasing voltage.

11. The memory system of claim 1 , wherein the temperature-dependent biasing circuit is a diode connected flash or floating-gate transistor.

12. The memory system of claim 1 , wherein the temperature-dependent biasing circuit includes a buffer configured to increase the driving capability of the biasing circuit.

13. The memory system of claim 1 , wherein the memory cells are programmable with analog (multi-bit) or digital values.

14. The memory system of claim 1 , wherein the memory cells are flash or floating-gate transistors.

15. The memory system of claim 1 , wherein the memory cells are configured to be biased to operate at different operating regimes including subthreshold, saturation, or triode (linear).

16. A memory system having a temperature effect compensation mechanism, the system comprising:

a plurality of memory cells organized in an array having a first row of two or more electrically coupled memory cells arranged horizontally and a second row of two or more electrically coupled memory cells arranged horizontally;

a first temperature-dependent biasing circuit having a first I-V curve configured to sense a temperature of the memory cells in the first row; and

a second temperature-dependent biasing circuit having a second I-V curve configured to sense a temperature of the memory cells in the second row,

wherein the first temperature-dependent biasing circuit is configured to change a biasing voltage applied to the first row of memory cells based on a temperature of the memory cells in the first row and wherein the second temperature-dependent biasing circuit is configured to change a biasing voltage applied to the second row of memory cells based on a temperature of the memory cells in the second row.

17. The memory system of claim 16 , wherein:

the plurality of memory cells has an operating temperature range,

the first temperature-dependent biasing circuit is configured to reduce the biasing voltage applied to the first row of memory cells when the temperature of the memory cells in the first row is at or near an upper end of the operating temperature range and increase the biasing voltage applied to the first row of memory cells when the temperature of the memory cells in the first row is at or near a lower end of the operating temperature range, and

the second temperature-dependent biasing circuit is configured to reduce the biasing voltage applied to the second row of memory cells when the temperature of the memory cells in the second row is at or near an upper end of the operating temperature range and increase the biasing voltage applied to the second row of memory cells when the temperature of the memory cells in the second row is at or near a lower end of the operating temperature range.

18. The memory system of claim 16 , wherein the first row of two or more electrically coupled memory cells includes an extra input configured to turn on and off the memory cells in the first row during either a read or write operation.

19. The memory system of claim 16 , wherein analog or digital inputs are applied to the extra input.