Wiring substrate, semiconductor package and method of manufacturing wiring substrate
A second wiring layer is connected to a first wiring layer via an insulating layer. The second wiring layer comprises pad structures. Each pad structure includes a first metal layer formed on the insulating layer, a second metal layer formed on the first metal layer, and a third metal layer formed on the second metal layer. The pad structures comprises a first pad structure and a second pad structure. A via-wiring diameter of the first pad structure is different from a via-wiring diameter of the second pad structure. A distance from an upper surface of the insulating layer to an upper surface of the second metal layer of the first pad structure is the same as a distance from the upper surface of the insulating layer to an upper surface of the second metal layer of the second pad structure.
1. A wiring substrate comprising:
a first wiring layer;
an insulating layer formed to cover the first wiring layer; and
a second wiring layer connected to the first wiring layer via the insulating layer,
wherein the second wiring layer comprises a plurality of pad structures, each of the pad structures including a via-wiring and a pad for semiconductor chip connection, the via-wiring filled in a via-hole, the via hole penetrating the insulating layer and formed to expose an upper surface of the first wiring layer, the pad for semiconductor chip connection formed on an upper surface of the insulating layer and integrally formed with the via-wiring,
wherein each of the pad structures comprises:
a first metal layer continuously formed on the upper surface of the insulating layer, on an inner wall surface of the via-hole, and on the upper surface of the first wiring layer exposed in the via-hole,
a second metal layer formed on the first metal layer, filling the via-hole, extending upwardly beyond the upper surface of the insulating layer, and having an upper surface being flat, and
a third metal layer formed on an upper surface of the second metal layer,
wherein the plurality of pad structures comprises a first pad structure and a second pad structure, and a via-wiring diameter of the first pad structure is different from a via-wiring diameter of the second pad structure, and
wherein a distance from the upper surface of the insulating layer to the upper surface of the second metal layer of the first pad structure is the same as a distance from the upper surface of the insulating layer to the upper surface of the second metal layer of the second pad structure.
2. The wiring substrate according to claim 1 , wherein a pad diameter of the first pad structure is different from a pad diameter of the second pad structure.
3. The wiring substrate according to claim 1 , wherein the second metal layer and the third metal layer are formed of a same metal material.
4. The wiring substrate according to claim 3 , wherein in each of the pad structure, the third metal layer and a part of the second metal layer forming the pad have a same area of a cross-section taken along a direction orthogonal to a direction in which the second metal layer and the third metal layer are stacked.
5. The wiring substrate according to claim 1 , wherein in a direction in which the second metal layer and the third metal layer are stacked, a part of the second metal layer forming the pad is thicker than the first metal layer.
6. A semiconductor package comprising:
the wiring substrate according to claim 1 ; and
a semiconductor chip mounted on the wiring substrate,
wherein the pads of the wiring substrate and electrode pads of the semiconductor chip are interconnected by soldering.