Pixel circuit

1. A pixel circuit, comprising:

a photodiode (PD), arranged to accumulate charges in response to incident radiation, to generate a PD signal;

a transmission circuit, coupled between the PD and an ordinary floating diffusion (FD) node, arranged to transmit the PD signal to the ordinary FD node;

a reset circuit, coupled to the ordinary FD node, arranged to reset the ordinary FD node and provide a reference signal;

a signal storage circuit, coupled to the ordinary FD node, arranged to store the PD signal on a specific node having a reduced leakage path in comparison with the ordinary FD node during a holding phase of the pixel circuit, wherein the holding phase is a time interval starting from a first time point at which the PD signal is stored on the specific node and ending at a second time point at which the pixel circuit is selected for performing a read-out operation; and

a buffer circuit, coupled to the ordinary FD node, arranged to buffer pixel signals of the pixel circuit, to generate output signals for being read out when the pixel circuit is selected for performing the read-out operation, wherein the pixel signals comprise the PD signal and the reference signal;

wherein the signal storage circuit comprises:

a first switch circuit, directly coupled between the ordinary FD node and a first FD node; and

a first capacitor, coupled between the first FD node and a voltage control node;

a second switch circuit, directly coupled between the ordinary FD node and a second FD node; and

a second capacitor, coupled between the second FD node and a voltage control node;

wherein:

one of the first FD node and the second FD node is arranged to store the PD signal, and another one of the first FD node and the second FD node is arranged to store the reference signal; and

each of the first switch circuit and the second switch circuit comprises at least one transistor.

2. The pixel circuit of claim 1 , wherein the buffer circuit comprises:

a source follower, comprising a first transistor, arranged to transmit the pixel signals from a gate terminal of the transistor to a source terminal of the transistor, to generate the output signals; and

a selecting circuit, comprising at least one transistor, coupled between the source terminal of the first transistor and an output terminal, arranged to output the output signals of the pixel circuit when the pixel circuit is selected for performing the read-out operation.

3. The pixel circuit of claim 1 , wherein each of the transmission circuit and the reset circuit comprises at least one transistor.

4. The pixel circuit of claim 1 , wherein the reset circuit resets the ordinary FD node during the holding phase of the pixel circuit.

5. The pixel circuit of claim 1 , wherein a voltage drop is applied to the voltage control node during the holding phase, to pull down a voltage level of the PD signal stored on the one of the first FD node and the second FD node during the holding phase, and to pull down a voltage level of the reference signal stored on said another one of the first FD node and the second FD node during the holding phase.

6. The pixel circuit of claim 5 , wherein the ordinary FD node, the reset circuit and the buffer circuit are shared with one or more nearby pixel circuits.

7. The pixel circuit of claim 1 , wherein the ordinary FD node, the reset circuit and the buffer circuit are shared with one or more nearby pixel circuits.