System and method for a lightweight fencing operation
A system and method for a lightweight fence is described. In particular, micro-operations including a fencing micro-operation are dispatched to a load queue. The fencing micro-operation allows micro-operations younger than the fencing micro-operation to execute, where the micro-operations are related to a type of fencing micro-operation. The fencing micro-operation is executed if the fencing micro-operation is the oldest memory access micro-operation, where the oldest memory access micro-operation is related to the type of fencing micro-operation. The fencing micro-operation determines whether micro-operations younger than the fencing micro-operation have load ordering violations and if load ordering violations are detected, the fencing micro-operation signals the retire queue that instructions younger than the fencing micro-operation should be flushed. The instructions to be flushed should include all micro-operations with load ordering violations.
1. A method for processing micro-operations, the method comprising:
dispatching micro-operations including a fencing micro-operation to a load queue;
executing one or more micro-operations younger than the fencing micro-operation, wherein the one or more micro-operations are each respectively fenced by one of a plurality of types of fencing micro-operation;
executing the fencing micro-operation in response to the fencing micro-operation being an oldest memory access micro-operation, wherein the oldest memory access micro-operation is fenced by a particular type of the fencing micro-operation; and
in response to detecting a load ordering violation:
instructing a retire queue to flush instructions younger than the fencing micro-operation, and
restarting execution at an oldest flushed instruction from the retire queue.
2. The method of claim 1 , wherein the fencing micro-operation waits in the load queue until all older memory access micro-operations have executed or completed, wherein the older micro-operations are fenced by the particular type of the fencing micro-operation.
3. The method of claim 1 , wherein in response to not detecting a load ordering violation for a second fencing micro-operation:
completing the second fencing micro-operation.
4. The method of claim 1 , wherein the retire queue includes micro-operations having load ordering violations.
5. The method of claim 1 , wherein the particular type of the fencing micro-operation is a load fencing micro-operation, and executing the fencing micro-operation in response to the fencing operation being an oldest memory access micro-operation comprises executing the fencing micro-operation in response to the load fencing micro-operation being an oldest load micro-operation in the load queue and allowing micro-operations younger than the load fencing micro-operation to execute or complete.
6. The method of claim 1 , wherein the particular type of the fencing micro-operation is a memory fencing micro-operation, and executing the fencing micro-operation in response to the fencing micro-operation being an oldest memory access micro-operation comprises executing the fencing operation in response to the memory fencing micro-operation being an oldest applicable memory access micro-operation and allowing non-store micro-operations younger than the memory fencing micro-operation to execute or complete.
7. The method of claim 1 , wherein the particular type of the fencing micro-operation is a memory fencing micro-operation, and executing the fencing micro-operation in response to the fencing micro-operation being an oldest memory access micro-operation comprises executing the fencing operation in response to older load micro-operations and older store micro-operations being executed or completed and allowing non-store micro-operations younger than the memory fencing micro-operation to execute or complete.
8. The method of claim 1 , wherein the particular type of the fencing micro-operation is a memory fencing micro-operation, and executing the fencing micro-operation in response to the fencing micro-operation being an oldest memory access micro-operation comprises executing the fencing operation in response to older load micro-operations and older store micro-operations being executed or completed and allowing non-store micro-operations younger than the memory fencing micro-operation to execute or complete.
9. The method of claim 1 , wherein control bits are set in a load micro-operation to indicate that the load micro-operation is the fencing micro-operation.
10. A processor for processing micro-operations, comprising:
an execution unit configured to dispatch micro-operations from a micro-op queue including a fencing micro-operation to a load queue, wherein the execution unit configured to:
execute one or more micro-operations younger than the fencing micro-operation, wherein the one or more micro-operations are each respectively fenced by one of a plurality of types of fencing micro-operation;
execute the fencing micro-operation in response to the fencing operation being an oldest memory access micro-operation, wherein the oldest memory access micro-operation is fenced by a particular type of the fencing micro-operation; and
in response to detecting a load ordering violation:
instruct a retire queue to flush younger instructions than the fencing micro-operation, and
restart execution at an oldest flushed instruction from the retire queue.
11. The processor of claim 10 , wherein the fencing micro-operation waits in the load queue until all older memory access micro-operations have executed or completed, wherein the older micro-operations are fenced by the particular type of the fencing micro-operation.
12. The processor of claim 10 , wherein in response to not detecting a load ordering violation for a second fencing micro-operation:
the second fencing micro-operation is completed.
13. The processor of claim 10 , wherein the particular type of the fencing micro-operation is a load fencing micro-operation, and executing the fencing micro-operation in response to the fencing operation being an oldest memory access micro-operation comprises executing the fencing micro-operation in response to the load fencing micro-operation being an oldest load micro-operation in the load queue and allowing micro-operations younger than the load fencing micro-operation to execute or complete.
14. The processor of claim 10 , wherein the particular type of the fencing micro-operation is a load fencing micro-operation, and executing the fencing micro-operation in response to the fencing micro-operation being an oldest memory access micro-operation comprises executing the fencing micro-operation in response to older load micro-operations in the load queue being executed or completed and allowing micro-operations younger than the load fencing micro-operation to execute or complete.
15. The processor of claim 10 , wherein the particular type of the fencing micro-operation is a memory fencing micro-operation, and executing the fencing micro-operation in response to the fencing micro-operation being an oldest memory access micro-operation comprises executing the fencing operation in response to the memory fencing micro-operation being an oldest memory access micro-operation and allowing non-store micro-operations younger than the memory fencing micro-operation to execute or complete.
16. The processor of claim 10 , wherein the particular type of the fencing micro-operation is a memory fencing micro-operation, and executing the fencing micro-operation in response to the fencing micro-operation being an oldest memory access micro-operation comprises executing the fencing operation in response to older load micro-operations and older store micro-operations being executed or completed and allowing non-store micro-operations younger than the memory fencing micro-operation to execute or complete.
17. The processor of claim 10 , wherein control bits are set in a load micro-operation to indicate that the load micro-operation is the fencing micro-operation.
18. The processor of claim 10 , wherein the retire queue includes micro-operations having load ordering violations.
19. The method of claim 1 , wherein the plurality of types of fencing micro-operation include at least one of a load fencing micro-operation, a memory fencing micro-operation, and a store fencing micro-operation.
20. The processor of claim 10 , wherein the plurality of types of fencing micro-operation include at least one of a load fencing micro-operation, a memory fencing micro-operation, and a store fencing micro-operation.