Push pull ringing suppression circuit
A circuit is provide comprising a first input coupled to a transmit data input of a bus transceiver; and a first output coupled to a bus. The circuit is configured to be coupled in parallel with the bus transceiver. The circuit is further configured to, in response to a dominant to recessive transition on the transmit data input, lower an impedance of the bus.
1. A circuit comprising:
a first input coupled to a transmit data input of a bus transceiver; and
a first output coupled to a bus;
wherein the circuit is configured to be coupled in parallel with the bus transceiver and configured to, in response to a dominant to recessive transition on the transmit data input, lower an impedance of the bus by outputting a negative drive current to the bus.
2. The circuit of claim 1 wherein the negative drive current is a first drive signal to drive the bus to a low impedance state.
3. The circuit of any preceding claim comprising:
a controller configured to detect the transition on the transmit data input; and
a transmitter configured to output a first drive signal in response to the detected transition.
4. The circuit of claim 3 wherein the transmitter is coupled to the bus in anti-phase to the coupling of a transmitter of the bus transceiver to the bus.
5. The circuit of claim 3 , wherein the transmitter is configured to drive the bus in an opposite polarity to a transmitter of the bus transceiver circuit.
6. The circuit of claim 3 wherein the first drive signal corresponds to a drive current output by the transmitter.
7. The circuit of claim 3 wherein in response to the transition on the transmit data input, the controller is configured to control the transmitter to transition the first drive signal between a first value and a second value.
8. The circuit of claim 7 wherein the first value corresponds to a value of a second drive signal output by the bus transceiver when the bus is in a passive recessive state.
9. The circuit of claim 7 where the second value corresponds to a third value that is the value of the second drive signal output by the bus transceiver when the bus is in a dominant state, where the second and third values have equal magnitude but opposite polarity.
10. The circuit of claim 7 wherein the controller is configured to control the transmitter to transition the first drive signal between the first value and the second value for a first period of time in response to the transition.
11. The circuit of claim 10 wherein the first period of time corresponds to a period of time taken for the second drive signal to transition between the third value and the first value in response to the transition on the transmit data input.
12. The circuit of claim 7 wherein the controller is further configured to control the transmitter to output the first drive signal at the second value for a second period of time.
13. The circuit of claim 7 wherein the controller is further configured to control the first drive signal to transition from the second value towards the first value at a first rate of change.
14. The circuit of claim 13 wherein the first rate of change is configured to be less than a rate of change that would cause ringing.
15. An apparatus comprising:
a bus transceiver coupled to receive a transmit data input and to provide a drive signal to a bus; and
a circuit including:
a first input coupled to a transmit data input of a bus transceiver; and
a first output coupled to a bus;
wherein the circuit is configured to be coupled in parallel with the bus transceiver and configured to, in response to a dominant to recessive transition on the transmit data input, lower an impedance of the bus by outputting a negative drive current to the bus.
16. The circuit of claim 15 wherein the negative drive current is a first drive signal to drive the bus to a low impedance state.
17. The circuit of claim 15 further comprising:
a controller configured to detect the transition on the transmit data input; and
a transmitter configured to output a first drive signal in response to the detected transition.
18. The circuit of claim 17 wherein the transmitter is coupled to the bus in anti-phase to the coupling of a transmitter of the bus transceiver to the bus.
19. The circuit of claim 17 , wherein the transmitter is configured to drive the bus in an opposite polarity to a transmitter of the bus transceiver circuit.
20. The circuit of claim 17 wherein the first drive signal corresponds to a drive current output by the transmitter.