Integrated circuit device

1. An integrated circuit device comprising:

a conductive line formed on a substrate;

an insulating spacer covering side walls of the conductive line and extending parallel with the conductive line; and

a conductive plug that is spaced apart from the conductive line with the insulating spacer therebetween,

wherein the insulating spacer comprises:

an insulating liner contacting the conductive line;

an outer spacer contacting the conductive plug; and

a barrier layer having a first portion between the insulating liner and the outer spacer to prevent oxygen atoms from diffusing into the outer spacer, and

wherein the barrier layer further includes a second portion which contacts a bottom surface of the outer spacer.

2. The integrated circuit device of claim 1 ,

wherein the barrier layer includes a two-dimensional material having a two-dimensional crystalline structure.

3. The integrated circuit device of claim 1 ,

wherein the barrier layer includes SiC, SiCN, or BN.

4. The integrated circuit device of claim 1 ,

wherein the insulating spacer further comprises an air spacer between the insulating liner and the barrier layer.

5. The integrated circuit device of claim 1 ,

wherein the barrier layer has a band gap of at least 1.3 eV.

6. The integrated circuit device of claim 1 ,

wherein the barrier layer includes a monomolecular layer of a two-dimensional material selected from among hexagonal boron nitride (h-BN), GaS, GaSe, phosphorene, WS 2 , WSe 2 , MoS 2 , MoSe 2 , ReS 2 , and ReSe 2 .

7. The integrated circuit device of claim 1 , wherein

the barrier layer has a thickness of 3 Å to 10 Å in a width direction of the conductive line.

8. An integrated circuit device comprising:

a line structure including a bit line formed on a substrate and an insulation capping pattern covering the bit line;

an insulating spacer covering side walls of the line structure;

a conductive plug spaced apart from the bit line in a first horizontal direction with the insulating spacer therebetween; and

a conductive landing pad vertically overlapping the conductive plug,

wherein the insulating spacer comprises:

an insulating liner including a first portion contacting the line structure and a second portion contacting the conductive plug;

an outer spacer contacting the conductive plug and the conductive landing pad; and

a barrier layer including a first portion between the insulating liner and the outer spacer to prevent oxygen atoms from diffusing into the outer spacer, and

wherein the barrier layer further includes a second portion which contacts a bottom surface of the outer spacer.

9. The integrated circuit device of claim 8 ,

wherein the barrier layer includes a two-dimensional material having a band gap of at least 1.3 eV, and

wherein the barrier layer is between the bit line and the conductive plug and between the insulation capping pattern and the conductive landing pad.

10. The integrated circuit device of claim 8 ,

wherein the two dimensional material of the barrier layer includes SiC, SiCN, or BN, and

wherein the barrier layer is between the bit line and the conductive plug and between the insulation capping pattern and the conductive landing pad.

11. The integrated circuit device of claim 8 ,

wherein the insulating spacer further comprises an air spacer, and

wherein the insulating liner is spaced apart from the first portion of the barrier layer with the air spacer therebetween.

12. The integrated circuit device of claim 8 , wherein

wherein the barrier layer includes a monomolecular layer of a two-dimensional material selected from among h-BN, GaS, GaSe, phosphorene, WS 2 , WSe 2 , MoS 2 , MoSe 2 , ReS 2 , and ReSe 2 .

13. The integrated circuit device of claim 8 ,

wherein the barrier layer includes a plurality of monomolecular layers of a two-dimensional material selected from among h-BN, GaS, GaSe, phosphorene, WS 2 , WSe 2 , MoS 2 , MoSe 2 , ReS 2 , and ReSe 2 .

14. The integrated circuit device of claim 8 ,

wherein the insulating liner includes a silicon nitride layer, and

wherein the outer spacer includes a silicon nitride layer doped with dopants of oxygen atoms (O), carbon atoms (C), or a combination of the above atoms.

15. An integrated circuit device comprising:

a line structure including a bit line formed on a substrate and an insulation capping pattern that covers the bit line;

a pair of insulating spacers covering opposite side walls of the line structure, respectively; and

a pair of conductive plugs spaced apart from each other in a first horizontal direction with the line structure and the pair of insulating spacers therebetween,

wherein each of the pair of insulating spacers comprises:

an insulating liner contacting the bit line;

an outer spacer contacting one of the pair of conductive plugs;

an outer barrier layer including a first portion between the insulating liner and the outer spacer to prevent oxygen atoms from diffusing into the outer spacer; and

an air spacer between the insulating liner and the outer barrier layer, and

wherein the outer barrier layer further includes a second portion which contacts a bottom surface of the outer spacer.

16. The integrated circuit device of claim 15 ,

wherein the insulating liner includes a silicon nitride layer,

wherein the outer spacer includes a silicon nitride layer doped with dopants of oxygen atoms (O), carbon atoms (C), or a combination of the above atoms, and

wherein the outer barrier layer includes a two-dimensional material having a band gap of at least 1.3 eV.

17. The integrated circuit device of claim 15 ,

wherein the insulating liner includes a silicon nitride layer,

wherein the outer spacer includes a silicon nitride layer doped with dopants of oxygen atoms (O), carbon atoms (C), or a combination of the above atoms, and

wherein the outer barrier layer includes SiC, SiCN, or BN.

18. The integrated circuit device of claim 15 ,

wherein the outer barrier layer includes a two-dimensional material selected from among h-BN, GaS, GaSe, phosphorene, WS 2 , WSe 2 , MoS 2 , MoSe 2 , ReS 2 , and ReSe 2 .

19. The integrated circuit device of claim 15 ,

wherein the outer barrier layer has a thickness between 3 Å and 10 Å in the first horizontal direction.

20. The integrated circuit device of claim 15 ,

wherein each of the pair of insulating spacers further comprises an inner barrier layer including the same material as the outer barrier layer,

the inner barrier layer contacts the insulating liner, and

the air spacer is between the inner barrier layer and the outer barrier layer.