Gate induced drain leakage reduction in FinFETs
A method of forming a semiconductor device that includes forming an inner dielectric spacer and outer dielectric spacer combination structure on a sacrificial gate structure that is present on a fin structure, wherein the inner dielectric spacer and outer dielectric spacer combination structure separates source and drain regions from the sacrificial gate structure. The method further includes removing the inner sidewall dielectric spacer; and forming a channel epitaxial wrap around layer on the portion of the fin structure that is exposed by removing the inner sidewall dielectric spacer. The method further includes removing the sacrificial gate structure to provide a gate opening to a channel portion of the fin structure, wherein the gate opening exposes the channel epitaxial wrap around layer; and forming a functional gate structure within the gate opening.
1. A method of forming a semiconductor device comprising:
forming an inner dielectric spacer and outer dielectric spacer combination structure on a sacrificial gate structure that is present on a fin structure, wherein the inner dielectric spacer and outer dielectric spacer combination structure separates source and drain regions from the sacrificial gate structure;
removing the inner sidewall dielectric spacer;
forming a channel epitaxial wrap around layer on the portion of the fin structure that is exposed by removing the inner sidewall dielectric spacer;
removing the sacrificial gate structure to provide a gate opening to a channel portion of the fin structure, wherein the gate opening exposes the channel epitaxial wrap around layer; and
forming a functional gate structure within the gate opening.
2. The method of claim 1 , wherein the channel epitaxial wrap around layer is present on sidewall and upper surfaces of the fin structure within the gate opening.
3. The method of claim 2 , wherein the channel epitaxial wrap around layer is a continuous and conformal epitaxially formed layer.
4. The method of claim 3 , wherein the channel epitaxial wrap around layer has a thickness of less than 5 nm.
5. The method of claim 3 , wherein when the fin structure is composed of silicon (Si), and the source and drain regions are n-type doped, the channel epitaxial wrap around layer is composed of silicon doped with carbon (Si:C).
6. The method of claim 3 , wherein the fin structure is composed of silicon (Si), and the source and drain region are p-type, the channel epitaxial wrap around layer is composed of silicon germanium (SiGe).
7. The method of claim 1 , wherein the channel epitaxial wrap around layer reduces gate induced drain leakage (GIDL).
8. The method of claim 1 , wherein the channel epitaxial wrap around layer is formed directly on an exterior surface of the fin structure.
9. A method of forming a semiconductor device comprising:
forming an inner dielectric spacer and outer dielectric spacer combination structure on a sacrificial gate structure that is present on a fin structure, wherein the inner dielectric spacer and outer dielectric spacer combination structure separates source and drain regions from the sacrificial gate structure;
removing the inner sidewall dielectric spacer;
forming a recess in the portion of the fin structure that is exposed by removing the inner sidewall dielectric spacer;
forming a channel epitaxial wrap around layer in the recess on the portion of the fin structure that is exposed by removing the inner sidewall dielectric spacer;
removing the sacrificial gate structure to provide a gate opening to a channel portion of the fin structure, wherein the gate opening exposes the channel epitaxial wrap around layer; and
forming a functional gate structure within the gate opening.
10. The method of claim 9 , wherein the channel epitaxial wrap around layer is present on sidewall and upper surfaces of the fin structure within the gate opening.
11. The method of claim 9 , wherein the channel epitaxial wrap around layer is a continuous and conformal epitaxially formed layer.
12. The method of claim 9 , wherein the recess is present on sidewall and upper surfaces of the fin structure within the gate opening.
13. The method of claim 9 , wherein the recess has a depth of less than 5 nm.
14. The method of claim 13 , wherein the channel epitaxial wrap around layer has a thickness of less than 5 nm.
15. The method of claim 9 , wherein when the fin structure is composed of silicon (Si), and the source and drain regions are n-type doped, the channel epitaxial wrap around layer is composed of silicon doped with carbon (Si:C).
16. The method of claim 9 , wherein the fin structure is composed of silicon (Si), and the source and drain region are p-type, the channel epitaxial wrap around layer is composed of silicon germanium (SiGe).
17. The method of claim 9 , wherein the channel epitaxial wrap around layer reduces gate induced drain leakage (GIDL).