Devices, structures, materials and methods for vertical light emitting transistors and light emitting displays
Devices, structures, materials and methods for vertical light emitting transistors (VLETs) and light emitting displays (LEDs) are provided. In particular, architectures for vertical polymer light emitting transistors (VPLETs) for active matrix organic light emitting displays (AMOLEDs) and AMOLEDs incorporating such VPLETs are described. Porous conductive transparent electrodes (such as from nanowires (NW)) alone or in combination with conjugated light emitting polymers (LEPs) and dielectric materials are utilized in forming organic light emitting transistors (OLETs). Combinations of thin films of ionic gels, LEDs, porous conductive electrodes and relevant substrates and gates are utilized to construct LETs, including singly and doubly gated VPLETs. In addition, printing processes are utilized to deposit layers of one or more of porous conductive electrodes, LEDs, and dielectric materials on various substrates to construct LETs, including singly and doubly gated VPLETs.
1. A vertical light emitting transistor, comprising:
a light emitting cell comprised of a light emitting layer formed of at least one light emitting material, the light emitting layer having first and second sides in conductive relation to a conductive drain electrode and a conductive source electrode;
at least one capacitor comprised of a dielectric layer formed of at least one dielectric material, the at least one dielectric layer having first and second sides in conductive relation to one of either the conductive source or drain electrodes, and a conductive gate electrode; and
at least one substrate in supportive relation with each of said drain and gate electrodes;
wherein the drain and source electrodes are the cathode and anode of the light emitting cell; and
wherein at least the electrode disposed between the light emitting layer and the dielectric layer is a conductive porous electrode has sufficient open portions to exhibit a surface coverage of no greater than 50%, such that the dielectric layer makes direct contact with the light emitting layer through the open portions of the conductive porous electrode.
2. The vertical light emitting transistor of claim 1 , wherein the vertical light emitting transistor comprises at least two capacitors and two gate electrodes, a first capacitor having a dielectric layer disposed between the drain electrode and a first gate electrode and a second capacitor disposed between the source electrode and a second gate electrode; and
wherein the drain and source electrodes are conductive porous electrodes that have sufficient open portions to exhibit a surface coverage of no greater than 50%, such that both of the dielectric layers make direct contact with the light emitting layer through the open portions of the conductive porous electrodes.
3. The vertical light emitting transistor of claim 1 , wherein the light emitting layer is formed of a light emitting material selected from the group consisting of a crystalline semiconductor selected from GaN, GaP, GaAs, AlGaAs, GaAsP, AlGaInP, ZnSe, InGaN and AIN; a semiconductor nanowire selected from Si and GaAs; a quantum wall; an organometallic complex; an Ir organometallic complex; a small organic conjugated molecule; porphyrin; pentacene; and a conjugated polymer selected from PPV, PVK, MEH-PPV, PPF, PFO and PPP.
4. The vertical light emitting transistor of claim 1 , wherein at least one of the drain, source, or gate electrodes comprise an electrode material selected from graphene sheets, doped Si, ZTO, ITO, Au, Al, Cu, Ni, Mo, Cr, Ag, metal nanowires, metal plate, metal meshes, metal grids, holey copper, holey graphene, conductive polymers, and a low coverage network of a plurality of nanowires.
5. The vertical light emitting transistor of claim 1 , wherein the at least one conductive porous electrode is formed from a plurality of nanowires formed into one of the group of a random or patterned network of a plurality of metal or graphene nanowires, a nanowire metal mesh, a nanowire grid, and a nanowire network encased within an elastomeric material.
6. The vertical light emitting transistor of claim 5 , wherein the plurality of nanowires are formed from a plurality of metal nanowires selected from Ag, Au and Cu having an aspect ratio of at least 1000.
7. The vertical light emitting transistor of claim 6 , wherein the plurality of metal nanowires have a diameter less than about 200 nm and a length greater than about 1 micron, and having a surface coverage less than 10%, a sheet resistance less than 100Ω/sq and a transmission greater than 75%.
8. The vertical light emitting transistor of claim 1 , wherein the dielectric material is selected from the group of an oxides selected from SiO 2 , Al 2 O 3 , HfO 2 , ZrO 2 ; a nitride; Si 3 N 4 ; an inorganic salts selected from LiF, CsF, BaTiO 3 , and SrTiO 3 ; a dielectric polymer selected from PMMA, Teflon, CYTOP, and Nafion; and an ionic gel formed from the combination of a dielectric polymer and an ionic liquid.
9. The vertical light emitting transistor of claim 1 , further comprising at least one additional light emitting enhancement layer selected from the group consisting of electron injection dipole layers, transportation dipole layers, conjugate polyelectrolyte layers, and hole injection layers.
10. The vertical light emitting transistor of claim 1 , wherein the substrate is selected from the group consisting of flexible plastics, Si wafer, glass, sapphire, and ITO.