Unconfined buried interconnects
View Patent ↗Embodiments of the present invention are directed to fabrication methods and resulting semiconductor structures having a bulb-shaped buried interconnect positioned below a shallow trench isolation region. In a non-limiting embodiment of the invention, a cavity is formed below a surface of a substrate. The cavity extends under a portion of a semiconductor fin. The cavity is filled with a sacrificial material and a shallow trench isolation region is formed on the sacrificial material in the cavity. A portion of the shallow trench isolation region is removed to expose a surface of the sacrificial material in the cavity. The sacrificial material is removed from the cavity and replaced with a buried interconnect.
1. A method for forming a buried interconnect structure, the method comprising:
forming a cavity below a surface of a substrate, the cavity extending under a portion of a semiconductor fin;
forming a shallow trench isolation region above the cavity;
removing a portion of the shallow trench isolation region to expose a top surface of a sacrificial material in the cavity; and
forming a buried interconnect in the cavity.
2. The method of claim 1 , wherein forming the cavity comprises an isotropic etch.
3. The method of claim 2 , wherein the cavity comprises a bulb-shaped region.
4. The method of claim 3 , wherein the bulb-shaped region undercuts the semiconductor fin by 50 to 250 nm from a sidewall of the semiconductor fin.
5. The method of claim 1 further comprising forming a liner in the cavity between a sacrificial material and the substrate.
6. The method of claim 1 further comprising forming a sacrificial gate over a channel region of the semiconductor fin, the cavity extending under a portion of the sacrificial gate.
7. The method of claim 6 further comprising forming an interlayer dielectric over the shallow trench isolation region and adjacent to the sacrificial gate.
8. The method of claim 7 further comprising replacing the sacrificial gate with a conductive gate.
9. The method of claim 1 , wherein at least a portion of the buried interconnect is positioned directly below the shallow trench isolation region, and wherein a portion of the buried interconnect extends beyond a sidewall of the shallow trench isolation region.
10. A method for forming a semiconductor structure, the method comprising:
forming a gate over a channel region of a substrate;
forming a cavity below a surface of the substrate, the cavity extending under the channel region;
filling the cavity with a sacrificial material;
forming a shallow trench isolation region on the sacrificial material in the cavity;
removing a portion of the shallow trench isolation region to expose a surface of the sacrificial material in the cavity; and
replacing the sacrificial material with a buried interconnect.
11. The method of claim 10 , wherein forming the cavity comprises an isotropic etch.
12. The method of claim 11 , wherein the cavity comprises a bulb-shaped region.
13. The method of claim 10 further comprising forming a liner in the cavity between the sacrificial material and the substrate.
14. The method of claim 10 , wherein the gate is a sacrificial gate.
15. The method of claim 14 further comprising replacing the sacrificial gate with a conductive gate.
16. The method of claim 10 further comprising forming an interlayer dielectric over the shallow trench isolation region and adjacent to the sacrificial gate.