Display device including polycrystalline silicon layer, method of manufacturing polycrystalline silicon layer, and method of manufacturing display device
A display device may include a thin film transistor disposed on a substrate, and a display element electrically connected to the thin film transistor. The thin film transistor may include an active pattern including polycrystalline silicon, a gate insulation layer disposed on the active pattern, and a gate electrode disposed on the gate insulation layer. An average value of grain sizes of the active pattern may be in a range of about 400 nm to about 800 nm. An RMS value of a surface roughness of the active pattern may be about 4 nm or less. A method of manufacturing a polycrystalline silicon layer may include cleaning an amorphous silicon layer with hydrofluoric acid, rinsing the amorphous silicon layer with hydrogenated deionized water, and irradiating the amorphous silicon layer with a laser beam having an energy density of about 440 mJ/cm 2 to about 490 mJ/cm 2 .
1. A display device, comprising:
a substrate;
a thin film transistor disposed on the substrate; and
a display element electrically connected to the thin film transistor,
wherein the thin film transistor comprises:
an active pattern disposed on the substrate, the active pattern including polycrystalline silicon;
an insulation layer disposed on the active pattern; and
a gate electrode disposed on the insulation layer, wherein
the active pattern comprises grains, and an average size of the grains is in a range of about 400 nm to about 800 nm, and
the active pattern comprises a rough surface of which roughness has a root-mean-square value equal to or less than about 4 nm.
2. A display device, comprising:
a substrate;
a thin film transistor disposed on the substrate; and
a display element electrically connected to the thin film transistor,
wherein the thin film transistor comprises:
an active pattern disposed on the substrate, the active pattern including polycrystalline silicon;
an insulation layer disposed on the active pattern; and
a gate electrode disposed on the insulation layer, wherein
the active pattern comprises grains, and an average size of the grains is in a range of about 400 nm to about 800 nm, and
the active pattern comprises a surface on which a protrusion is formed between adjacent ones of the grains, and a thickness of the protrusion is about 4 nm or less.
3. The display device of claim 2 , wherein the thickness of the protrusion corresponds to a distance between a top of the protrusion and a surface of the active pattern in a grain adjacent to the protrusion.
4. The display device of claim 1 , wherein the active pattern comprises grain boundaries each of which is formed between adjacent ones of the grains, and a size of a grain corresponds to a distance between adjacent grain boundaries of the grain.
5. The display device of claim 1 , wherein each grain includes one or more crystal planes, and a ratio of a (111) direction crystal plane to total crystal planes of the active pattern is greater than a ratio of a (001) direction crystal plane to the total crystal planes.
6. The display device of claim 1 , wherein a value obtained by dividing a sum of a ratio of a (001) direction crystal plane to total crystal planes of the active pattern and a ratio of a (101) direction crystal plane to the total crystal planes by a ratio of a (111) direction crystal plane to the total crystal planes is about 0.7 or less.
7. The display device of claim 1 , wherein the display element comprises:
a first electrode electrically connected to the thin film transistor;
an emission layer disposed on the first electrode; and
a second electrode disposed on the emission layer.