IP Library › Granted Patent US 11,189,492
Granted Patent B2
US 11,189,492 · App. 17/025,753 · Granted Nov 30, 2021

Semiconductor structure and fabrication method thereof

Inventors: Zhang Pan (Shanghai, CN); Ting Zhang (Shanghai, CN)
Assignees: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufacturing International (Beijing) Corporation
H01L21/0337H01L21/0332H01L21/31116
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Quick Facts
Patent No.
US 11,189,492
App. No.
17/025,753
Granted
Nov 30, 2021
Kind
B2
Abstract

A semiconductor structure and its fabrication method are provided in the present disclosure. The method includes providing a base substrate, forming a plurality of discrete core layers on the base substrate, forming an isolation layer on a top surface of a core layer, forming a sacrificial layer on the base substrate and exposing a top surface of the isolation layer, removing the isolation layer after forming the sacrificial layer, removing the sacrificial layer after removing the isolation layer, forming a mask layer on a sidewall surface of the core layer after removing the sacrificial layer, and removing the core layer after forming the mask layer.

Claims (51)

1. A method for fabricating a semiconductor structure, comprising:

providing a base substrate;

forming a plurality of discrete core layers on the base substrate;

forming an isolation layer on a top surface of a core layer;

forming a sacrificial layer on the base substrate and exposing a top surface of the isolation layer;

after forming the sacrificial layer, removing the isolation layer;

after removing the isolation layer, removing the sacrificial layer;

after removing the sacrificial layer, forming a mask layer on a sidewall surface of the core layer; and

after forming the mask layer, removing the core layer.

2. The method according to claim 1 , wherein:

the isolation layer is made of a material including silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

3. The method according to claim 1 , wherein forming the sacrificial layer includes:

forming a sacrificial film on the base substrate, wherein the sacrificial film covers the top surface and a sidewall surface of the isolation layer; and

etching back the sacrificial film to form the sacrificial layer, wherein a top surface of the sacrificial layer is coplanar with or lower than a bottom surface of the isolation layer.

4. The method according to claim 3 , wherein:

the sacrificial film is made of a material including a photoresist material or an organic material containing carbon and oxygen.

5. The method according to claim 1 , wherein forming the mask layer includes:

forming a mask material layer on a surface of the base substrate, wherein the mask material layer covers the top surface and the sidewall surface of the core layer; and

etching back the mask material layer till the surface of the base substrate and the top surface of the core layer are exposed to form the mask layer.

6. The method according to claim 1 , wherein:

the core layer is made of a material including amorphous silicon, amorphous carbon, polysilicon, or a combination thereof.

7. The method according to claim 1 , further including:

before forming the sacrificial layer, forming a first protection layer on the sidewall surface of the core layer, wherein a material of the mask layer is different from a material of the first protection layer; and

after removing the core layer, removing the first protection layer.

8. The method according to claim 1 , further including:

after forming the mask layer and before removing the core layer, forming a second protection layer on a sidewall surface of the mask layer, wherein a material of the second protection layer is different from a material of the mask layer; and

removing the second protection layer after removing the core layer.

9. The method according to claim 8 , wherein:

a first etching process is used to remove a first protection layer and the second protection layer;

an etching rate of the first protection layer is greater than an etching rate of the mask layer by the first etching process; and

an etching rate of the second protection layer is greater than the etching rate of the mask layer by the first etching process.

10. The method according to claim 7 , wherein:

the first protection layer is made of a material including silicon oxide, silicon nitride, silicon carbide nitride, silicon boride nitride, silicon carbide oxygen nitride, silicon nitride oxide, or a combination thereof.

11. The method according to claim 7 , wherein:

a thickness of the first protection layer is from about 10 angstroms to about 20 angstroms.

12. The method according to claim 7 , wherein:

the first protection layer is formed by a process including an in-situ steam generation process, a chemical vapor deposition process, a physical vapor deposition process, or a combination thereof.

13. The method according to claim 8 , wherein:

the second protection layer is made of a material including silicon oxide, silicon nitride, silicon carbide nitride, silicon boride nitride, silicon carbide oxygen nitride, silicon nitride oxide, or a combination thereof.

14. The method according to claim 8 , wherein:

a thickness of the second protection layer is greater than 20 angstroms and less than a half of a distance between adjacent mask layers.

15. The method according to claim 8 , wherein:

the second protection layer is formed by a process including a furnace tube process, a chemical vapor deposition process, a physical vapor deposition process, or a combination thereof.

16. The method according to claim 1 , wherein removing the core layer includes:

using a second etching process to remove the core layer; and after removing the core layer, using a third etching process to remove etching by-products generated during the second etching process.

17. The method according to claim 16 , wherein:

the second etching process is a dry etching process; and the third etching process is a wet etching process.

18. The method according to claim 8 , wherein:

the base substrate includes a substrate and a hard mask layer on a surface of the substrate.

19. The method according to claim 18 , further including:

after removing the first protection layer and the second protection layer, etching the base substrate using the mask layer as a mask.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 18, 2020
From: PAN, ZHANG; ZHANG, TING
To: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION; SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
Reel/Frame 053821/0806 →
Priority Claims (1)
CN 201910919338.X · Sep 26, 2019 · national
Continuity (1)
Related Publication 20210098256A1 · Apr 1, 2021