Semiconductor device and method of manufacturing the same
In a method of forming a semiconductor device including a fin field effect transistor (FinFET), a first sacrificial layer is formed over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is patterned, thereby forming an opening. A first liner layer is formed on the isolation insulating layer in a bottom of opening and at least side faces of the patterned first sacrificial layer. After the first liner layer is formed, a dielectric layer is formed in the opening. After the dielectric layer is formed, the patterned first sacrificial layer is removed, thereby forming a contact opening over the source/drain structure. A conductive layer is formed in the contact opening.
1. A semiconductor device including fin field effect transistors (FinFETs), comprising:
an isolation insulating layer disposed over a substrate;
a first FinFET including a first fin structure extending in a first direction, a first source/drain structure and a first source/drain contact in contact with the first source/drain structure, a channel region of the first fin structure protruding from the isolation insulating layer;
a second FinFET disposed adjacent to the first FinFET and including a second fin structure extending in the first direction, a second source/drain structure and a second source/drain contact in contact with the second source/drain structure, a channel region of the second fin structure protruding from the isolation insulating layer; and
a dielectric layer separating the first source/drain contact and the second source/drain contact,
wherein two layers are disposed between a bottom of the dielectric layer and an upper surface of the isolation insulating layer.
2. The semiconductor device of claim 1 , wherein at least one of the two layers s made of silicon nitride.
3. The semiconductor device of claim 1 , wherein:
the two layers include a first layer disposed on the isolation insulating layer and a second layer disposed on the first layer, and
in a cross section along a second direction crossing the first direction, the second layer has a U-shape cross section and the first layer has a line-shape cross section.
4. The semiconductor device of claim 3 , wherein in the cross section, a width of the first layer is smaller than a width of the dielectric layer.
5. The semiconductor device of claim 4 , wherein a thickness of the second layer is greater than a thickness of the first layer.
6. The semiconductor device of claim 1 , further comprising a residual piece of a semiconductor material disposed at a bottom corner of the dielectric layer.
7. The semiconductor device of claim 6 , wherein the residual piece of the semiconductor material includes amorphous silicon or polysilicon.
8. The semiconductor device of claim 1 , wherein the first source/drain structure includes an epitaxial layer formed around a source/drain region of the first fin structure that protrudes from the isolation insulating layer.
9. The semiconductor device of claim 8 , wherein the first source/drain structure further includes a silicide layer disposed between the epitaxial layer and the first source/drain contact.
10. A semiconductor device including fin field effect transistors (FinFETs), comprising:
an isolation insulating layer disposed over a substrate;
a first FinFET including a first fin structure extending in a first direction, a first source/drain structure and a first source/drain contact in contact with the first source/drain structure, a channel region of the first fin structure protruding from the isolation insulating layer;
a second FinFET disposed adjacent to the first FinFET and including a second fin structure extending in the first direction, a second source/drain structure and a second source/drain contact in contact with the second source/drain structure, a channel region of the second fin structure protruding from the isolation insulating layer; and
a dielectric layer separating the first source/drain contact and the second source/drain contact,
wherein two layers are disposed between a bottom of the dielectric layer and an upper surface of the isolation insulating layer, and
a part of the first source/drain contact penetrate into the bottom of the dielectric layer.
11. The semiconductor device of claim 10 , wherein the first source/drain contact is not in direct contact with the dielectric layer.
12. The semiconductor device of claim 10 , wherein the first source/drain contact is not in direct contact with the two layers.
13. The semiconductor device of claim 10 , wherein a width of at least one of the first source/drain contact and the second source/drain contact along a second direction crossing the first direction varies along a vertical direction perpendicular to a surface the substrate.
14. The semiconductor device of claim 13 , wherein the width decreases as a distance from the substrate increases.
15. A semiconductor device including fin field effect transistors (FinFETs), comprising:
an isolation insulating layer disposed over a substrate;
a first FinFET including a first fin structure extending in a first direction, a first source/drain structure and a first source/drain contact in contact with the first source/drain structure, a channel region of the first fin structure protruding from the isolation insulating layer;
a second FinFET disposed adjacent to the first FinFET and including a second fin structure extending in the first direction, a second source/drain structure and a second source/drain contact in contact with the second source/drain structure, a channel region of the second fin structure protruding from the isolation insulating layer; and
a dielectric layer separating the first source/drain contact and the second source/drain contact,
wherein two layers are disposed between a bottom of the dielectric layer and an upper surface of the isolation insulating layer,
at least one of the first and second source/drain contacts includes a lower portion and an upper portion having a funnel shape, and
a width of the upper portion is greater than a width of the bottom portion.
16. The semiconductor device of claim 15 , wherein the width of the bottom portion is constant.
17. The semiconductor device of claim 15 , wherein a difference between the width of the upper portion and the width of the bottom portion is less than 6 nm.
18. The semiconductor device of claim 15 , wherein a vertical length of the bottom portion is greater than a vertical length of the upper portion.
19. The semiconductor device of claim 15 , wherein the vertical length of the bottom portion is twice or more the vertical length of the upper portion.
20. The semiconductor device of claim 15 , wherein:
the first FinFET further includes a gate electrode, and
an interface between the bottom portion and the upper portion is located at a level higher than an upper surface of the gate electrode.