Semiconductor structure with raised implanted region and manufacturing method thereof

1. A semiconductor structure, comprising:

a metallization structure having a top surface;

a conductive pad over the top surface of the metallization structure;

an upper passivation layer over the top surface of the metallization structure, a sidewall of the conductive pad, and a top surface of the conductive pad, wherein the upper passivation layer comprises:

a raised portion conformal to and in direct contact with the sidewall of the conductive pad, the raised portion comprising an implanted region; and

a plain portion away from the conductive pad and being free from having the implanted region;

a polymer layer over the upper passivation layer and the conductive pad; and

a conductive via penetrating through the upper passivation layer and the polymer layer, electrically coupled to the conductive pad.

2. The semiconductor structure of claim 1 , wherein the implanted region comprises a first implanted region adjacent to a lower sidewall of the conductive pad.

3. The semiconductor structure of claim 1 , wherein the implanted region comprises a second implanted region adjacent to an upper sidewall of the conductive pad.

4. The semiconductor structure of claim 1 , further comprising a lower passivation layer under the conductive pad and the upper passivation layer.

5. The semiconductor structure of claim 4 , further comprising a passive device in the lower passivation layer.

6. The semiconductor structure of claim 1 , wherein the upper passivation layer comprises an oxide layer and a nitride layer.

7. The semiconductor structure of claim 1 , wherein a coefficient of thermal expansion (CTE) of the conductive pad is closer to a CTE of the implanted region than to a CTE of the upper passivation layer away from the implanted region.

8. The semiconductor structure of claim 1 , wherein the implanted region comprises germanium, and a concentration of the germanium in the implanted region is in a range of from about 1.0E14/cm 3 to about 1.0E15/cm 3 .

9. A semiconductor structure, comprising:

a metallization structure having a top surface;

a metal-insulator-metal (MIM) structure over the top surface;

a conductive pad over the MIM structure;

an upper passivation layer covering a sidewall of the conductive pad, the upper passivation layer comprises:

a raised portion conformal to and in direct contact with the sidewall of the conductive pad, the raised portion comprising a plurality of dopants; and

a plain portion away from the conductive pad and being free from having the plurality of dopants; and

a conductive bump penetrating through the upper passivation layer, electrically coupled to the conductive pad.

10. The semiconductor structure of claim 9 , wherein the upper passivation layer further comprises a silicon oxide layer in contact with the sidewall of the conductive pad.

11. The semiconductor structure of claim 10 , wherein an atomic order of each of the plurality of dopants is greater than an atomic order of silicon or oxygen.

12. The semiconductor structure of claim 10 , wherein the upper passivation layer further comprises a silicon nitride layer covering the silicon oxide layer, the silicon nitride layer comprises the plurality of dopants.

13. The semiconductor structure of claim 9 , wherein the plurality of dopants are located adjacent to a bottom sidewall of the conductive pad.

14. The semiconductor structure of claim 9 , wherein the MIM structure comprises a super high density MIM structure at least partially overlapping with the conductive pad.

15. A method for manufacturing a semiconductor structure, comprising:

providing a metallization structure having a top surface;

forming a conductive pad over the top surface;

forming an upper passivation layer over the top surface of the metallization structure and the conductive pad, and the upper passivation layer comprises a raised portion conformal to and in direct contact with a sidewall of the conductive pad, and a plain portion away from the conductive pad; and

implanting a plurality of dopants only in the raised portion of the upper passivation layer.

16. The method of claim 15 , wherein an implanting angle between an implanting direction and a normal of the top surface is in a range of from about 40 degrees to about 50 degrees.

17. The method of claim 15 , further comprising:

forming an opening over the conductive pad and penetrating through the upper passivation layer; and

forming a conductive bump in the opening and electrically coupled to the conductive pad.

18. The method of claim 15 , wherein forming the upper passivation layer comprises:

forming an oxide layer over the conductive pad;

implanting the plurality of dopants in the oxide layer; and

forming a nitride layer over the oxide layer.

19. The method of claim 18 , further comprising:

implanting the plurality of dopants in the nitride layer.

20. The method of claim 15 , further comprising:

forming a lower passivation layer prior to forming the conductive pad, the lower passivation layer comprising a high density metal-insulator-metal (MIM) structure.