Process etch with reduced loading effect
A grating structure has a plurality of grating members that extend upward from a base in a spaced-apart parallel relationship and include an end member. For example, the grating structure is a plurality of semiconductor fins on a base. The base can be any structure underlying the grating members. The grating members have a member width and a member height. Adjacent grating members are spaced by a grating spacing. A process artifact is adjacent the end member and is spaced from the end member by a horizontal distance consistent with the member spacing. In some cases, the process artifact can be a stub of a second material on or otherwise extending from the base adjacent an end member of the grating structure. In other cases, the process artifact can be a recess in or otherwise extending into the base adjacent an end member of the grating structure.
1. An integrated circuit comprising:
a grating structure comprising a first semiconductor material and having a plurality of grating members including an end member, members of the plurality of grating members extending upward from a base in a spaced-apart parallel relationship and defining a member width, a member height, and a member spacing between adjacent members of the plurality of grating members; and a process artifact adjacent the end member, wherein the process artifact is spaced from the end member by a horizontal distance from 50% to 200% of the member spacing, and wherein the process artifact is a stub of a second material extending from the base, the second material being compositionally different from the first semiconductor material.
2. The integrated circuit of claim 1 , wherein the second material comprising (i) a metal, (ii) amorphous carbon, (iii) aluminum and oxygen, (iv) silicon and oxygen; (v) hafnium and oxygen, or (vi) silicon and nitrogen.
3. An integrated circuit with a grating structure, the grating structure comprising:
a plurality of tins comprising a first material, the plurality of tins extending upward from a base in a spaced-apart, generally parallel relationship, wherein fins of the plurality of fins have a fin width, a fin height, and a fin spacing between adjacent fins, and wherein the plurality of fins includes an end fin adjacent only one of the plurality of fins; a process artifact horizontally spaced no more than twice the in spacing from a bottom end portion of the end fin, the process artifact comprising a stub of a second material extending from the base, the second material being compositionally different from the first material.
4. The integrated circuit of claim 3 , wherein the process artifact is spaced from the end fin by a distance from 90% to 110% of the fin spacing.
5. The integrated circuit of claim 3 , wherein the stub of the second material defines at least one peak.
6. The integrated circuit of claim 3 , wherein the fin height is greater than 50 nm.
7. The integrated circuit of claim 6 , wherein the fin width of any one fin of the plurality of fins differs by no more than two nm along a 25 nm tall portion of the one fin.
8. The integrated circuit of claim 6 , wherein the fin width of any one fin of the plurality of fins differs by no more than one nm along a 25 nm tall portion of the one fin.
9. The integrated circuit of claim 8 , wherein the fin width is 8 nm or less at a location that is 10 nm or more from a top of the one fin and 10 nm or more from a bottom of the one fin.
10. The integrated circuit of claim 3 , wherein the first material comprises a Group IV semiconductor material or a Group III-V semiconductor material.
11. The integrated circuit of claim 3 , wherein the process artifact has an artifact width at least as great as the fin width.
12. The integrated circuit of claim 3 further comprising a layer of isolation material on the base in contact with a lower portion of the plurality of fins.
13. The integrated circuit of claim 3 further comprising a gate structure in contact with a portion of fins of the plurality of fins, the gate structure including a gate electrode and a gate dielectric between the first material and the gate electrode, wherein the portion is between a source region and a drain region.
14. The integrated circuit of claim 3 further comprising a source contact on the source region and a drain contact on the drain region.
15. The integrated circuit of claim 3 , wherein the grating structure is a first grating structure and the integrated circuit further comprises a second grating structure spaced from the first grating structure by more than twice the fin spacing, the second grating structure including a second plurality of fins, wherein fins of the second plurality of fins have a second fin width, a second fin height, and a second fin spacing between adjacent fins, and wherein the second plurality of fins includes a second end fin adjacent only one of the second plurality of fins;
wherein the processing artifact is positioned between the first grating structure and the second grating structure and horizontally spaced no more than twice the second fin spacing from a lower end portion of an end fin of the second grating structure.