VFET standard cell architecture with improved contact and super via
A cell architecture for vertical field-effect transistors (VFETs) is provided. The cell architecture includes: top source/drain (S/D) contact structure having a square shape in a plan view; and horizontal metal patterns formed on the top S/D contact structures and extended in an X-direction to be connected to a vertical pattern through with an output signal of a logic circuit formed by the VFETs. The cell architecture further includes a gate contact structure formed on a gate connection pattern connecting gates of the VFETs, wherein a super via is formed on the gate contact structure to receive an input signal of the logic circuit.
1. A cell architecture comprising:
a plurality of vertical field-effect transistors (VFETs) formed on a substrate to constitute a logic circuit;
a 1 st top source/drain (S/D) contact structure formed on a 1 st top S/D region of a 1 st VFET and connected to a 1 st horizontal metal pattern formed thereon and extended in an X-direction of the cell architecture to connect an output signal of the logic circuit output from the 1 st top S/D region to a 1 st vertical metal pattern;
a 2 nd top S/D contact structure formed on a 2 nd top S/D region of a 2 nd VFET and connected to a 2 nd horizontal metal pattern formed thereon and extended in the X-direction to connect the output signal of the logic circuit output from the 2 nd top S/D region to the 1 st vertical metal pattern; and
a gate contact structure formed on a gate connection pattern connected to respective gates of the 1 st and 2 nd VFETs, the gate contact structure being connected to an input signal of the logic circuit through a super via,
wherein the 1 st VFET and the 2 nd VFET are formed along a 1 st fin structure extended in a Y-direction of the cell architecture, and
wherein both of the 1 st top S/D contact structure and the 2 nd top S/D contact structure have a substantially-square shape in a plan view of the cell architecture.
2. The cell architecture of claim 1 , wherein the super via is connected to a 2 nd vertical metal pattern to which the input signal of the logic circuit is input, and
wherein the 1 st horizontal metal pattern and the 2 nd horizontal metal pattern are connected to the 1 st vertical metal pattern through a 1 st via and a 2 nd via, respectively.
3. The cell architecture of claim 2 , wherein the 1 st vertical metal pattern and the 2 nd vertical metal pattern are parallel to each other without overlapping each other in the plan view of the cell architecture, and are disposed on a same level from an upper surface of the substrate.
4. The cell architecture of claim 3 , wherein upper surfaces of the 1 st top S/D contact structure, the 2 nd top S/D contact structure and the gate contact structure are disposed on a same level from the upper surface of the substrate.
5. The cell architecture of claim 4 , wherein a height of the super via is the same as a sum of heights of the 1 st via and the 1 st horizontal metal pattern.
6. The cell architecture of claim 4 , wherein the 1 st top S/D contact structure is connected to the 1 st horizontal metal pattern through a 3 rd via formed thereon, and the 2 nd top S/D contact structure is connected to the 2 nd horizontal metal pattern through a 4 th via formed thereon.
7. The cell architecture of claim 6 , wherein a height of the super via is the same as a sum of heights of the 1 st via, the 1 st horizontal metal pattern and the 3 rd via.
8. The cell architecture of claim 1 , further comprising a 3 rd top S/D contact structure formed on a 3 rd top S/D region of a 3 rd VFET and extended to an edge of the cell architecture to be connected to a power rail,
wherein an upper surface of the 3 rd top S/D contact structure is spaced apart from a lower surface of the 1 st horizontal metal pattern.
9. The cell architecture of claim 8 , further comprising a 4 th top S/D contact structure formed on a 4 th top S/D region of a 4 th VFET and connected to the 2 nd horizontal metal pattern formed thereon and extended in the X-direction to connect the output signal of the logic circuit to the 1 st vertical metal pattern through a 2 nd via.
10. The cell architecture of claim 9 , wherein the 3 rd VFET and the 4 th VFET are formed on a 2 nd fin structure extended in parallel with the 1 st fin structure,
wherein the 1 st vertical metal pattern, through which the output signal of the logic circuit is transmitted out, is formed between the 1 st fin structure and the 2 nd fin structure.