IP Library Granted Patent US 11,189,723
Granted Patent B2
US 11,189,723 · App. 17/081,607 · Granted Nov 30, 2021

Semiconductor device

Inventor: Yasuyuki Hoshi (Matsumoto, JP)
Assignee: FUJI ELECTRIC CO., LTD.
H01L29/7813H01L29/1608H01L29/4236H01L29/66734
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Quick Facts
Patent No.
US 11,189,723
App. No.
17/081,607
Granted
Nov 30, 2021
Kind
B2
Abstract

A semiconductor device including a semiconductor substrate, a first semiconductor layer provided on a main surface of the semiconductor substrate, a second semiconductor layer selectively provided on a surface of the first semiconductor layer, a plurality of first and second semiconductor regions selectively provided in the second semiconductor layer at a surface thereof, and a plurality of trenches provided in a striped pattern that extends in a first direction. The first semiconductor regions include a plurality of connecting parts and a plurality of non-connecting parts that are alternately arranged in the first direction, each connecting part being continuous in a second direction orthogonal to the first direction, and each non-connecting part being separated into two halves in the second direction by one of the second semiconductor regions, each half including a plurality of regions having different resistance values, disposed in a descending order or an ascending order of the resistance values along the first direction.

Claims (20)

1. A semiconductor device, comprising:

a semiconductor substrate of a first conductivity type, having a first main surface and a second main surface opposite to each other;

a first semiconductor layer of the first conductivity type, provided on the first main surface of the semiconductor substrate and having an impurity concentration lower than an impurity concentration of the semiconductor substrate, the first semiconductor layer having a first surface and a second surface opposite to each other, the second surface facing the semiconductor substrate;

a second semiconductor layer of a second conductivity type, selectively provided on the first surface of the first semiconductor layer, the second semiconductor layer having a first surface and a second surface opposite to each other, the second surface facing the semiconductor substrate;

a plurality of first semiconductor regions of the first conductivity type, selectively provided in the second semiconductor layer at the first surface thereof;

a plurality of second semiconductor regions of the second conductivity type, selectively provided in the second semiconductor layer at the first surface thereof, to be in contact with the first semiconductor regions;

a plurality of trenches provided in a striped pattern that extends in a first direction, penetrating the first semiconductor regions and the second semiconductor layer, and reaching the first semiconductor layer;

a plurality of gate electrodes respectively provided in the trenches via a gate insulating film;

a plurality of first electrodes provided on surfaces of the first semiconductor regions and the second semiconductor regions; and

a second electrode provided on the second main surface of the semiconductor substrate, wherein

the first semiconductor regions include a plurality of connecting parts and a plurality of non-connecting parts that are alternately arranged in the first direction, each connecting part being continuous in a second direction orthogonal to the first direction, and each non-connecting part being separated into two halves in the second direction by one of the second semiconductor regions, each half including a plurality of regions having different resistance values, disposed in a descending order or an ascending order of the resistance values along the first direction,

the first electrodes are in contact with the first semiconductor regions through the connecting parts of the first semiconductor regions.

2. The semiconductor device according to claim 1 , wherein

in said each half, the plurality of regions have a plurality of widths in the second direction, the widths changing stepwise along the first direction.

3. The semiconductor device according to claim 1 , wherein

in said each half, the plurality of regions include three regions, which are a high-resistance region, an intermediate-resistance region, and a low-resistance region that are disposed sequentially.

4. The semiconductor device according to claim 1 , wherein

one of the non-connecting parts is separated by one of the second semiconductor regions that is of a diamond-shape, a diagonal of which connects midpoints of the one non-connecting part in a plan view.

5. The semiconductor device according to claim 1 , wherein

the plurality of regions having the different resistance values are periodically disposed along the first direction.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 27, 2020
From: HOSHI, YASUYUKI
To: FUJI ELECTRIC CO., LTD.
Reel/Frame 054184/0026 →
Priority Claims (1)
JP JP2019-223280 · Dec 10, 2019 · national
Continuity (1)
Related Publication 20210175353A1 · Jun 10, 2021