Thin-film transistors with low contact resistance
Techniques are disclosed for forming thin-film transistors (TFTs) with low contact resistance. As disclosed in the present application, the low contact resistance can be achieved by intentionally thinning one or both of the source/drain (S/D) regions of the thin-film layer of the TFT device. As the TFT layer may have an initial thickness in the range of 20-65 nm, the techniques for thinning the S/D regions of the TFT layer described herein may reduce the thickness in one or both of those S/D regions to a resulting thickness of 3-10 nm, for example. Intentionally thinning one or both of the S/D regions of the TFT layer induces more electrostatic charges inside the thinned S/D region, thereby increasing the effective dopant in that S/D region. The increase in effective dopant in the thinned S/D region helps lower the related contact resistance, thereby leading to enhanced overall device performance.
1. A transistor comprising:
a gate electrode including one or more metals;
a gate dielectric on the gate electrode;
a layer on the gate dielectric, the layer including one or more metals, the layer also including oxygen;
a first contact structure on the layer, the first contact structure including one or more metals, a first portion of the layer between the first contact structure and the gate dielectric; and
a second contact structure on the layer, the second contact structure including one or more metals, a second portion of the layer between the second contact structure and the gate dielectric;
wherein the first portion of the layer has a first thickness, the second portion of the layer has a second thickness, and a third portion of the layer between the first and second portions of the layer has a third thickness, the third thickness at least 10 nanometers (nm) greater than one or both of the first thickness or the second thickness.
2. The transistor of claim 1 , wherein the one or more metals included in the layer includes at least one of indium, gallium, or zinc.
3. The transistor of claim 1 , wherein the one or more metals included in the layer includes indium, gallium, and zinc.
4. The transistor of claim 1 , wherein the gate dielectric includes one or more high-k dielectric materials.
5. The transistor of claim 1 , wherein the gate dielectric includes hafnium and oxygen.
6. The transistor of claim 1 , wherein the gate dielectric includes one or both of silicon dioxide or low-k dielectric material.
7. The transistor of claim 1 , wherein the gate dielectric includes a thickness between the gate electrode and the layer of at least 5 nm.
8. The transistor of claim 1 , wherein one or both of the first thickness or the second thickness is at most 10 nm.
9. The transistor of any of claim 1 , further comprising:
an additional gate dielectric on a side of the layer opposite the gate dielectric; and
an additional gate electrode on the additional gate dielectric, the additional gate electrode including one or more metals.
10. The transistor of any of claim 1 , wherein the one or more metals and the oxygen included in the layer are included throughout the entirety of the layer.
11. The transistor of any of claim 1 , wherein the layer is a multilayer structure including at least two compositionally different sub-layers, individual sub-layers including one or more metals, individual sub-layers also including oxygen.
12. The transistor of claim 11 , wherein the third portion of the layer includes at least one sub-layer that is absent in the first and second portions of the layer.
13. The transistor of any of claim 1 , wherein at least one material included in the third portion of the layer increases in content along the third thickness.
14. The transistor of any of claim 1 , wherein one or both of the first contact structure or the second contact structure extends past an end of the layer.
15. The transistor of any of claim 1 , wherein the first contact structure and the second contact structure are above the gate electrode.