Identifying software interaction defects using differential speed processors
Aspects of the invention include methods, systems and computer program products for identifying interaction software defects. Aspects include singly executing a first testcase at a normal processing speed and singly executing a second testcase at the normal processing speed. Aspects also include simultaneously executing the first testcase at a first processing speed and a second testcase at a second processing speed. Based on determining the single and simultaneous testcase results do not match, aspects further include creating an error notification.
1. A method for identifying interaction software defects, the method comprising:
singly executing a first testcase at a normal processing speed;
singly executing a second testcase at the normal processing speed;
simultaneously executing the first testcase at a first processing speed and a second testcase at a second processing speed;
based on determining the single and simultaneous testcase results do not match, creating an error notification; and
based on determining the single and simultaneous testcase results match, simultaneously executing the first testcase at a third processing speed and the second testcase at a fourth processing speed.
2. The method of claim 1 , wherein a processor speed is decreased by adding no-op instructions and the processor speed increased by removing no-op instructions.
3. The method of claim 1 , wherein the first and second processing speeds are different.
4. The method of claim 1 , wherein the first and second processing speeds are the same.
5. The method of claim 1 , wherein application instances singly execute with normal processing speed and simultaneously execute with different processor speeds.
6. The method of claim 1 , wherein single and simultaneous testcase errors create an error notification.
7. The method of claim 1 , wherein creating the error notification includes at least one of:
an error type detected and testcase identification;
single and simultaneous testcase results; and
single and simultaneous testcase processing speeds.
8. A system comprising:
one or more processors for executing computer-readable instructions, the computer-readable instructions controlling the one or more processors to perform operations comprising:
singly executing a first testcase at a normal processing speed;
singly executing a second testcase at the normal processing speed;
simultaneously executing the first testcase at a first processing speed and a second testcase at a second processing speed;
based on determining the single and simultaneous testcase results do not match, creating an error notification; and
based on determining the single and simultaneous testcase results match, simultaneously executing the first testcase at a third processing speed and the second testcase at a fourth processing speed.
9. The system of claim 8 , wherein a processor speed is decreased by adding no-op instructions and the processor speed increased by removing no-op instructions.
10. The system of claim 8 , wherein the first and second processing speeds are different.
11. The system of claim 8 , wherein the first and second processing speeds are the same.
12. The system of claim 8 , wherein application instances singly execute with normal processing speed and simultaneously execute with different processor speeds.
13. The system of claim 8 , wherein single and simultaneous testcase errors create an error notification.
14. The system of claim 8 , wherein creating the error notification includes at least one of:
an error type detected and testcase identification;
single and simultaneous testcase results; and
single and simultaneous testcase processing speeds.
15. A computer program product comprising a computer-readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to perform operations comprising:
singly executing a first testcase at a normal processing speed;
singly executing a second testcase at the normal processing speed;
simultaneously executing the first testcase at a first processing speed and a second testcase at a second processing speed;
based on determining the single and simultaneous testcase results do not match, creating an error notification; and
based on determining the single and simultaneous testcase results match, simultaneously executing the first testcase at a third processing speed and the second testcase at a fourth processing speed.
16. The computer program product of claim 15 , wherein a processor speed is decreased by adding no-op instructions and the processor speed increased by removing no-op instructions.
17. The computer program product of claim 15 , wherein the first and second processing speeds are different.