Victim cache that supports draining write-miss entries
A caching system including a first sub-cache and a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache includes a set of cache lines, line type bits configured to store an indication that a corresponding cache line of the set of cache lines is configured to store write-miss data, and an eviction controller configured to flush stored write-miss data based on the line type bits.
1. A caching system comprising:
a first level cache including:
a first sub-cache; and
a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache includes:
a set of cache lines;
line type bits configured to indicate a line type of a corresponding cache line of the set of cache lines, wherein a first line type is an indication that the cache line of the set of cache lines is configured to store a line of data evicted out of the first sub-cache, wherein a second line type is an indication that the corresponding cache line of the set of cache lines is configured to store write-miss data; and
an eviction controller configured to flush stored write-miss data based on the line type bits; and
a second level cache.
2. The caching system of claim 1 , wherein the second sub-cache further comprises:
a tag random access memory (RAM) configured to store a memory address associated with the stored write-miss data; and
a byte enable memory configured to store byte enable logic associated with the stored write-miss data, and
wherein the eviction controller is configured to flush stored write-miss data by transmitting a memory write request to a higher level memory based the stored memory address and stored byte enable logic.
3. The caching system of claim 1 , wherein the caching system further includes a processor interface, and wherein the eviction controller is further configured to:
monitor activity on the processor interface; and
flush stored write-miss data based on the monitored activity.
4. The caching system of claim 3 , wherein monitoring activity on the processor interface comprises detecting idle activity on the processor interface.
5. The caching system of claim 4 , wherein detecting idle activity comprises determining whether memory requests have been received for a predetermined number of clock cycles.
6. The caching system of claim 4 , wherein the eviction controller is further configured to:
determine that activity on the processor interface has resumed; and
cancel flushing of the stored write-miss data.
7. The caching system of claim 6 , wherein determining that activity on the processor interface has resumed comprises detecting a cache request receipt from the processor.
8. A method for caching data, comprising:
receiving, by a first level cache, a write memory request for a memory address;
determining, by a first sub-cache of the first level cache, that the memory address is not cached in the first sub-cache;
determining, by second sub-cache of the first level cache, that the memory address is not cached in the second sub-cache;
storing data associated with the write memory request in the second sub-cache;
storing, in a line type bit of the second sub-cache, an indication that the stored data corresponds to a write-miss;
monitoring, on a processor interface, activity of a processor; and
flushing the stored data based on the indication and the activity of the processor is at or below a threshold.
9. The method of claim 8 , wherein flushing the stored data comprises transmitting, by the second-sub cache, a memory write request to a higher level memory.
10. The method of claim 8 , wherein the threshold is idle activity on the processor interface.
11. The method of claim 10 , wherein detecting idle activity comprises determining that memory requests have not been received for a predetermined number of clock cycles.
12. The method of claim 10 , further comprising:
determining that activity on the processor interface has resumed; and
cancelling flushing of the stored write-miss data.
13. The method of claim 12 , wherein determining that activity on the processor interface has resumed comprises detecting a cache request receipt.
14. A device comprising:
a processor including a first level cache, wherein the first level cache includes:
a first sub-cache; and
a second sub-cache in parallel with the first sub-cache, wherein the second sub-cache includes:
a set of cache lines;
line type bits configured to indicate a line type of a corresponding cache line of the set of cache lines, wherein a first line type is an indication that the cache line of the set of cache lines is configured to store a line of data evicted out of the first sub-cache, wherein a second line type is an indication that the corresponding cache line of the set of cache lines is configured to store write-miss data; and
an eviction controller configured to flush stored write-miss data based on the line type bits.
15. The device of claim 14 , wherein the second sub-cache further comprises:
a tag random access memory (RAM) configured to store a memory address associated with the stored write-miss data; and
a byte enable memory configured to store byte enable logic associated with the stored write-miss data, and
wherein the eviction controller is configured to flush stored write-miss data by transmitting a memory write request to a higher level memory based the stored memory address and stored byte enable logic.
16. The device of claim 14 , wherein the caching system further includes a processor interface, and wherein the eviction controller is further configured to:
monitor activity on the processor interface; and
flush stored write-miss data based on the monitored activity.
17. The device of claim 16 , wherein monitoring activity on the processor interface comprises detecting idle activity on the processor interface.
18. The device of claim 17 , wherein detecting idle activity comprises determining whether memory requests have been received for a predetermined number of clock cycles.
19. The device of claim 17 , wherein the eviction controller is further configured to:
determine that activity on the processor interface has resumed; and
cancel flushing of the stored write-miss data.