Semiconductor integrated circuit device including an electro-static discharge protection circuit

1. A semiconductor integrated circuit device comprising:

a pad;

a first voltage protection circuit connected to the pad, the first voltage protection circuit being driven when a negative electrostatic charge flows into the first voltage protection circuit, the first voltage protection circuit including a gate positive p-channel metal oxide semiconductor (GPPMOS) transistor;

a second voltage protection circuit connected between the first voltage protection circuit and a ground terminal, the second voltage protection circuit being driven when a positive electrostatic charge flows into the second voltage protection circuit, the second voltage protection circuit including connected GPPMOS transistors in series; and

a revision circuit block selectively connected between the pad and any one of the connection nodes of the GPPMOS transistors of the second voltage protection circuit to change a transmission path of a voltage inputted from the pad.

2. The semiconductor integrated circuit device of claim 1 , wherein the revision circuit block comprises a revising circuit, and

the revising circuit is selectively opened or closed to change the transmission path of the voltage inputted from the pad.

3. The semiconductor integrated circuit device of claim 1 , wherein the GPPMOS transistor of the first voltage protection circuit is turned-on by generating a parasitic PNP bipolar transistor when a negative voltage is inputted from the pad, and the GPPMOS transistor of the first voltage protection circuit performs a forward diode operation when a positive voltage is inputted from the pad.

4. The semiconductor integrated circuit device of claim 1 , wherein each of the GPPMOS transistors of the first and second voltage protection circuits comprises:

an n-well formed on a semiconductor substrate;

a gate formed on the n-well;

a source formed in the n-well at one side of the gate; and

a drain formed in the n-well at an other side of the gate.

5. The semiconductor integrated circuit device of claim 4 , wherein the semiconductor substrate comprises a substrate including p-type impurities, and the n-well directly makes contact with the substrate including the p-type impurities.

6. The semiconductor integrated circuit device of claim 1 , wherein numbers of the GPPMOS transistors in the second voltage protection circuit are determined by changing the location of the connection node connected to the revision circuit block in accordance with a size of the positive electro-static voltage.

7. The semiconductor integrated circuit device of claim 1 , wherein the GPPMOS transistors of the second voltage protection circuit have substantially the same threshold voltage.

8. The semiconductor integrated circuit device of claim 1 , wherein the GPPMOS transistors of the second voltage protection circuit have gradually decreased threshold voltages.

9. The semiconductor integrated circuit device of claim 1 , wherein the GPPMOS transistor of the first voltage protection circuit comprises:

a drain connected to the pad; and

a gate and a source commonly connected with each other.

10. The semiconductor integrated circuit device of claim 9 , wherein each of the serially connected GPPMOS transistors of the second voltage protection circuit comprises:

a gate and a source commonly connected with each other; and

a drain connected to the source of a next GPPMOS transistor,

wherein any one of the GPPMOS transistors of the second voltage protection circuit comprises the source connected to the source of the first voltage protection circuit.

11. A semiconductor integrated circuit device comprising:

an electrostatic discharge (ESD) protection circuit, wherein the ESD protection circuit is turned-off when a normal voltage is applied from a pad, and the ESD protection circuit is driven by a voltage above and below the normal voltage, the ESD protection circuit comprising:

a first GPPMOS transistor connected to the pad;

a plurality of second GPPMOS transistors serially connected between the first GPPMOS transistor and a ground terminal; and

a revision circuit directly connected between any one of connection nodes among the plurality of second GPPMOS transistors and the ground terminal,

wherein a signal transmission path is selectively formed or blocked between the connection node of the plurality of second GPPMOS transistors and the ground terminal by the revision circuit.

12. The semiconductor integrated circuit device of claim 11 , wherein numbers of the serially connected the plurality of second GPPMOS transistors are determined in accordance with a trigger voltage of the GPPMOS transistor and an electro-static voltage.

13. The semiconductor integrated circuit device of claim 11 , wherein the first GPPMOS transistor and the plurality of second GPPMOS transistors are formed in separated n-wells directly making contact with a p-type semiconductor substrate.