Solid-state imaging device and imaging device with shared circuit elements
An imaging device includes a plurality of unit pixels disposed into pixel groups that are separated from one another by isolation structures. Unit pixels within each pixel group are separated from one another by isolation structures and share circuit elements. The isolation structures between pixel groups are full thickness isolation structures. At least a portion of the isolation structures between unit pixels within a pixel group are deep trench isolation structures.
1. An imaging device, comprising:
a pixel array unit, wherein the pixel array unit includes a plurality of pixel groups, wherein each pixel group includes:
a plurality of unit pixels, wherein the plurality of unit pixels includes at least first and second unit pixels;
a plurality of photoelectric conversion regions, wherein each unit pixel includes at least one of the photoelectric conversion regions;
a first readout circuit selectively coupled to the plurality of photoelectric conversion regions;
a second readout circuit selectively coupled to the plurality of photoelectric conversion regions; and
an isolation structure, wherein the isolation structure separates the first unit pixel from the second unit pixel, wherein each pixel group further includes a third unit pixel and a fourth unit pixel, and wherein the first, second, third and fourth unit pixels are disposed in a 2×2 array.
2. The imaging device of claim 1 , wherein the isolation structure includes a deep trench isolation structure portion.
3. The imaging device of claim 2 , wherein the isolation structure includes a full thickness trench isolation structure portion.
4. The imaging device of claim 2 , wherein the first readout circuit is an imaging signal generation circuit.
5. The imaging device of claim 4 , wherein the second readout circuit is an address event detection readout circuit.
6. The imaging device of claim 5 , further comprising:
a substrate, wherein the photoelectric conversion regions are formed in the substrate, wherein a first surface of the substrate is an incident light surface, wherein a second surface of the substrate is a non-incident light surface, and wherein at least a portion of an element of at least one of the first and second readout circuits is formed between an end of the deep trench isolation structure and the second surface of the substrate.
7. The imaging device of claim 1 , wherein the isolation structure is entirely a deep trench isolation structure.
8. The imaging device of claim 1 , wherein the second readout circuit is an address event detection readout circuit.
9. The imaging device of claim 1 , wherein each pixel group is separated from a neighbor pixel group by a full thickness trench isolation structure.
10. The imaging device of claim 9 , wherein the isolation structure that separates the first unit pixel from the second unit pixel is a first isolation structure, wherein the first isolation structure separates the third unit pixel from the fourth unit pixel, wherein a second isolation structure separates the first unit pixel from the third unit pixel, wherein the second isolation structure separates the second unit pixel from the fourth unit pixel, and wherein the second isolation structure intersects the first isolation structure.
11. The imaging device of claim 10 , wherein the first isolation structure is entirely a deep trench isolation structure, and wherein the second isolation structure is entirely a deep trench isolation structure.
12. The imaging device of claim 10 , wherein the first isolation structure is entirely a deep trench isolation structure, wherein at least a first portion of the second isolation structure is a deep trench isolation structure, and wherein at least a second portion of the second isolation structure is a full thickness isolation structure.
13. The imaging device of claim 10 , wherein at least a portion of the first isolation structure is a deep trench isolation structure, wherein at least a second portion of the first isolation structure is a full thickness isolation structure, and wherein the second isolation structure is entirely a deep trench isolation structure.
14. The imaging device of claim 10 , wherein at least a portion of the first isolation structure is a deep trench isolation structure, wherein at least a second portion of the first isolation structure is a full thickness isolation structure, wherein at least a first portion of the second isolation structure is a deep trench isolation structure, and wherein at least a second portion of the second isolation structure is a full thickness isolation structure.
15. An imaging device, comprising:
a pixel array unit, wherein the pixel array unit includes a plurality of pixel groups, wherein each pixel group includes:
a plurality of unit pixels, wherein the plurality of unit pixels includes at least first and second unit pixels;
a plurality of photoelectric conversion regions, wherein each unit pixel includes at least one of the photoelectric conversion regions;
a first readout circuit selectively coupled to the plurality of photoelectric conversion regions, wherein the first readout circuit is an imaging signal generation circuit;
a second readout circuit selectively coupled to the plurality of photoelectric conversion regions, wherein the second readout circuit is an address event detection readout circuit; and
an isolation structure, wherein the isolation structure separates the first unit pixel from the second unit pixel, wherein the isolation structure includes a deep trench isolation structure portion; and
a substrate, wherein the photoelectric conversion regions are formed in the substrate, wherein a first surface of the substrate is an incident light surface, wherein a second surface of the substrate is a non-incident light surface, wherein at least a portion of an element of at least one of the first and second readout circuits is formed between an end of the deep trench isolation structure and the second surface of the substrate, wherein the photoelectric conversion region of the first unit pixel is selectively connected to the imaging signal generation circuit by a first unit pixel transmission transistor and a pixel group transmission transistor, and wherein the photoelectric conversion region of the second unit pixel is selectively connected to the imaging signal generation circuit by a second unit pixel transmission transistor and the pixel group transmission transistor.
16. The imaging device of claim 15 , wherein the photoelectric conversion region of the first unit pixel is selectively connected to the address event detection readout circuit by the first unit pixel transmission transistor and a pixel group overflow gate transistor, and wherein the photoelectric conversion region of the second unit pixel is selectively connected to the address event detection readout circuit by the second unit pixel transmission transistor and the pixel group overflow gate transistor.
17. The imaging device of claim 15 , wherein the isolation structure is entirely a deep trench isolation structure.
18. An imaging device, comprising:
a pixel array unit, wherein the pixel array unit includes a plurality of pixel groups, wherein each pixel group includes:
a plurality of unit pixels, wherein the plurality of unit pixels includes at least first and second unit pixels;
a plurality of photoelectric conversion regions, wherein each unit pixel includes at least one of the photoelectric conversion regions;
a first readout circuit selectively coupled to the plurality of photoelectric conversion regions, wherein the first readout circuit is an imaging signal generation circuit;
a second readout circuit selectively coupled to the plurality of photoelectric conversion regions, wherein the second readout circuit is an address event detection readout circuit; and
an isolation structure, wherein the isolation structure separates the first unit pixel from the second unit pixel, wherein the isolation structure includes a deep trench isolation structure portion; and
a substrate, wherein the photoelectric conversion regions are formed in the substrate, wherein a first surface of the substrate is an incident light surface, wherein a second surface of the substrate is a non-incident light surface, wherein at least a portion of an element of at least one of the first and second readout circuits is formed between an end of the deep trench isolation structure and the second surface of the substrate, wherein the photoelectric conversion region of the first unit pixel is selectively connected to the imaging signal generation circuit by a first unit pixel transmission transistor, and wherein the photoelectric conversion region of the second unit pixel is selectively connected to the imaging signal generation circuit by a second unit pixel transmission transistor.
19. The imaging device of claim 18 , wherein the photoelectric conversion region of the first unit pixel is selectively connected to the address event detection readout circuit by a first unit pixel overflow gate transistor, and wherein the photoelectric conversion region of the second unit pixel is selectively connected to the address event detection readout circuit by a second unit pixel overflow gate transistor.
20. The imaging device of claim 18 , wherein the isolation structure is entirely a deep trench isolation structure.