IP Library › Granted Patent US 11,196,165
Granted Patent B2
US 11,196,165 · App. 16/017,093 · Granted Dec 7, 2021

Low z-height, ultra-low dielectric constant air cavity based and multi-core/highly asymmetric antenna substrate architectures for electrical performance improvements in 5G mm-wave applications

Inventors: Sri Chaitra Chavali (Chandler, AZ); Siddharth Alur (Chandler, AZ); Sheng Li (Gilbert, AZ)
Assignee: Intel Corporation
H01Q9/0414H01L23/66H01Q1/2283H01Q5/35H01Q9/0435H01L2223/6677
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Quick Facts
Patent No.
US 11,196,165
App. No.
16/017,093
Granted
Dec 7, 2021
Kind
B2
Abstract

Embodiments include antennas, methods of forming antennas, and a semiconductor package. An antenna includes a feed port disposed in a substrate, and the feed port having a first patch and a second patch. The first patch is disposed on a top surface of substrate, and the second patch is disposed on a bottom surface of substrate. The antenna includes a photoimageable dielectric (PID) disposed on the bottom surface of substrate, where PID surrounds the second patch. The antenna includes a third patch disposed on PID, where the third patch is below the second patch. The antenna includes a cavity disposed between the second and third patches, where the cavity is enclosed by PID and third patch. An additional antenna includes a patch disposed on a first substrate, and a feed port disposed in a second substrate. This antenna includes a composite layer disposed between the first and second substrates.

Claims (50)

1. An antenna, comprising:

a feed port in a substrate, the feed port having a first patch and a second patch, wherein the first patch is on a top surface of the substrate, and the second patch is on a bottom surface of the substrate;

a photoimageable dielectric (PID) on the bottom surface of the substrate, wherein the PID surrounds the second patch;

a third patch on the PID, wherein the third patch is below the second patch; and

a cavity between the second patch and the third patch, wherein the cavity is enclosed by the PID and the third patch.

2. The antenna of claim 1 , further comprising:

a first resist on the first patch of the feed port and the top surface of the substrate; and

a second resist on a bottom surface of the PID, wherein the second resist surrounds the third patch.

3. The antenna of claim 1 , wherein the substrate includes a core substrate and a coreless substrate.

4. The antenna of claim 1 , wherein the feed port further comprises:

plated through hole (PTH) vias coupled to the first patch and the second path; and

a resin disposed between the PTH vias and the first and second patches.

5. The antenna of claim 1 , wherein the third patch has a footprint that is greater than both the first patch and the second patch.

6. The antenna of claim 1 , wherein the cavity is an air cavity.

7. The antenna of claim 1 , wherein the cavity has a footprint that is approximately 4 mm by 4 mm or less.

8. The antenna of claim 1 , wherein the cavity isolates heat from traveling between the second patch and the third patch.

9. The antenna of claim 2 , wherein the first and second resists include photodefinable materials.

10. The antenna of claim 1 , wherein the first patch has a footprint that is approximately equal to a footprint of the second patch.

11. An antenna, comprising:

a patch on a first substrate;

a feed port in a second substrate, the feed port having a first patch and a second patch, wherein the first patch is on a top surface of the second substrate, and the second patch is on a bottom surface of the second substrate; and

a composite layer between the first substrate and the second substrate.

12. The antenna of claim 11 , wherein the composite layer attaches a bottom surface of the first substrate to the first patch of the feed port and the top surface of the second substrate.

13. The antenna of claim 11 , wherein the composite layer includes a core material and an ultra-low dielectric constant material.

14. The antenna of claim 11 , further comprising:

a first resist on the patch and a top surface of the first substrate; and

a second resist on a bottom surface of second substrate and the second patch.

15. The antenna of claim 11 , wherein the first substrate includes a core substrate and a coreless substrate.

16. The antenna of claim 11 , wherein the second substrate includes a core substrate and a coreless substrate.

17. The antenna of claim 11 , wherein the feed port further comprises:

plated through hole (PTH) vias coupled to the first patch and the second path; and

a resin disposed between the PTH vias and the first and second patches.

18. The antenna of claim 11 , wherein the first substrate has a thickness that is approximately equal to a thickness of the second substrate.

19. The antenna of claim 11 , wherein the composite layer is an adhesive.

20. The antenna of claim 13 , wherein the ultra-low dielectric constant material has a dielectric constant of approximately of 3 or less and a dielectric loss of approximately of 0.003 or less.

21. The antenna of claim 14 , wherein the first and second resists include photodefinable materials.

22. The antenna of claim 11 , wherein the patch has a footprint that is approximately equal to a footprint of the first patch and a footprint of the second patch, and wherein the first substrate has a thickness that is equal to a thickness of the second substrate.

23. A semiconductor package, comprising:

an interposer on a substrate; and

a die on the interposer; and

at least one of a first antenna and a second antenna on the substrate.

24. The semiconductor package of claim 23 , wherein the first antenna further comprises:

a feed port in a substrate, the feed port having a first patch and a second patch, wherein the first patch is on a top surface of the substrate, and the second patch is on a bottom surface of the substrate;

a photoimageable dielectric (PID) on the bottom surface of the substrate, wherein the PID surrounds the second patch;

a third patch on the PID, wherein the third patch is below the second patch; and

a cavity between the second patch and the third patch, wherein the cavity is enclosed by the PID and the third patch.

25. The semiconductor package of claim 24 , wherein the second antenna further comprises:

a patch on a first substrate;

a feed port in a second substrate, the feed port having a first patch and a second patch, wherein the first patch is on a top surface of the second substrate, and the second patch is on a bottom surface of the second substrate; and

a composite layer between the first substrate and the second substrate.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 25, 2018
From: CHAVALI, SRI CHAITRA; ALUR, SIDDHARTH; LI, SHENG
To: INTEL CORPORATION
Reel/Frame 046196/0479 →
Continuity (1)
Related Publication 20190393606A1 · Dec 26, 2019