IC dies with parallel PRBS testing of interposer

1. A microelectronic assembly that comprises:

a substrate electrically connected in a flip-chip configuration to an originating IC (integrated circuit) die and to a destination IC die,

the substrate having multiple conductive traces for a parallel communications bus between the originating and destination IC dies,

the originating IC die having a first parallel PRBS (pseudo-random binary sequence) generator to drive test PRBSs with different phases in parallel across the multiple conductive traces,

the destination IC die having:

a second parallel PRBS generator to create reference PRBSs with different phases; and

a bitwise comparator coupled to receive the test PRBSs from the multiple conductive traces and to compare the test PRBSs to the reference PRBSs to provide concurrent fault monitoring for each of the multiple conductive traces.

2. The assembly of claim 1 , wherein the test PRBSs are preceded by a start pattern having at least one “zero” sent simultaneously on each of the multiple conductive traces followed by a “one” sent simultaneously on each of the multiple conductive traces.

3. The assembly of claim 1 , wherein first parallel PRBS generator is iterated starting with a seed value, and wherein the second parallel PRBS generator is initialized with the seed value when a start pattern is detected on the multiple conductive traces.

4. The assembly of claim 1 , wherein the first and second parallel PRBS generators each provide echoed PRBSs for an expanded number of parallel sequences.

5. The assembly of claim 1 , wherein the parallel communications bus is N bits wide, and wherein the multiple conductive traces of the substrate include at least one extra trace to provide redundancy protection against a faulty trace.

6. The assembly of claim 5 , wherein each of the originating and destination IC dies includes a multiplexer array that enables signals for the parallel communications bus to be routed around the faulty trace.

7. The assembly of claim 6 , wherein the destination IC die includes a correction controller coupled to the bitwise comparator to identify which if any of the multiple conductive traces have a fault and to responsively determine a setting for at least one of the multiplexer arrays to route around the fault.

8. A microelectronic assembly test method that comprises:

receiving a start pattern synchronously on each of multiple interposer traces coupling an originating IC die to a destination IC die;

initializing a parallel PRBS generator upon detecting the start pattern;

performing a bitwise comparison of reference PRBSs from the parallel PRBS generator with test PRBSs received via the multiple interposer traces;

identifying which, if any, of the multiple interposer traces are faulty based on the bitwise comparison; and

if a faulty interposer trace is detected, configuring the originating IC die and the destination IC die to avoid use of the faulty interposer trace.

9. The method of claim 8 , wherein the start pattern comprises at least one “zero” sent simultaneously on each of the multiple interposer traces followed by a “one” sent simultaneously on each of the multiple interposer traces.

10. The method of claim 9 , wherein said initializing includes storing a predetermined seed value in a register as an initial state for the parallel PRBS generator.

11. The method of claim 10 , further comprising:

iterating to generate on each clock cycle a subsequent state from a present state in the register;

deriving from each bit in the register a corresponding one of the reference PRBSs; and

echoing at least one of the reference PRBSs derived from the register bits to provide at least one additional one of the reference PRBSs.

12. The method of claim 8 , wherein each of the originating and destination IC dies includes a multiplexer array, and wherein said configuring includes programming the multiplexer arrays to route communication signals around the faulty trace using one or more redundant interposer traces.

13. An IC die that comprises:

a set of input multiplexers that map N bits along N+1 interposer traces connecting said IC die to another IC die;

a set of test multiplexers that insert on each of said interposer traces a corresponding one of multiple test PRBSs; and

a parallel PRBS generator that provides the multiple test PRBSs in parallel to the set of test multiplexers, the multiple test PRBSs having different phases.

14. The IC die of claim 13 , further comprising:

a set of output multiplexers that map receive signals from N+1 interposer traces to N output bit lanes, the receive signals including incoming test PRBSs during testing; and

a bitwise comparator that compares each of the incoming test PRBSs with corresponding reference PRBSs.

15. The IC die of claim 14 , further comprising:

a second parallel PRBS generator that provides the reference PRBSs in parallel to the bitwise comparator, the reference PRBSs having different phases.

16. The IC die of claim 13 , wherein the parallel PRBS generator includes a preamble multiplexer to insert a start pattern ahead of the multiple test PRBSs.

17. The IC die of claim 16 , wherein the start patter comprises at least one “zero” sent simultaneously on each of the interposer traces followed by a “one” sent simultaneously on each of the interposer traces.

18. The IC die of claim 13 , wherein the parallel PRBS generator is initialized with a predetermined seed value.

19. The IC die of claim 13 , wherein the parallel PRBS generator echoes one or more of the multiple test PRBSs for an expanded number of parallel sequences.

20. The IC die of claim 13 , further comprising a set of latches driven synchronously by a clock signal that is also communicated via a dedicated interposer trace.