Method and apparatus for controlling different types of storage units
The invention introduces an apparatus for controlling different types of storage units, at least including: an interface and a processing unit. The interface connects at least two types of storage units, which include at least a nonvolatile hybrid memory. The processing unit is configured to operably access data to the different types of storage units through the interface.
1. An apparatus for controlling different types of storage units, comprising:
an interface connected to at least two different types of storage units wherein the storage units comprising a non-volatile hybrid memory; and
a processing unit coupled to the interface, arranged to
operably access data of the different types of the storage units through the interface;
during a system booting stage, initialize the non-volatile hybrid memory;
read a first parameter for configuring a flash memory, and an In-System Programming (ISP) code from the non-volatile hybrid memory;
initialize the flash memory according to the first parameter; and
execute the ISP code to enter a normal mode and wait for a command issued by a host.
2. The apparatus of claim 1 , wherein the non-volatile hybrid memory is a single level cell (SLC) flash memory, the storage units comprise a flash memory, the SLC flash memory stores parameters required for configuring the flash memory, and In-System Programming (ISP) code.
3. The apparatus of claim 2 , wherein the interface comprises a plurality of channels, each channel is connected to a flash module and a SLC flash module, the flash modules of different channels are enabled by a first signal, and the SLC flash modules of different channels are enabled by a second signal.
4. The apparatus of claim 3 , wherein the processing unit is arranged to operably configure the interface in an operating mode for accessing data of the flash module before enabling the flash module by the first signal; and configure the interface in an operating mode for accessing data of the SLC flash module before enabling the SLC flash module by the second signal.
5. The apparatus of claim 2 , wherein the interface comprises a first channel and a second channel, the first channel is connected to a flash module only, and the second channel is connected to a SLC flash module only.
6. The apparatus of claim 5 , wherein the processing unit comprises a first core and a second core, the first core is arranged to operably control the first channel and the second core is arranged to operably control the second channel.
7. The apparatus of claim 1 , wherein the hybrid memory is a Phase-Change Memory (PCM) or a magnetoresistive memory, the storage units comprise a Dynamic Random Access Memory (DRAM), the PCM or the magnetoresistive memory stores parameters required for configuring the DRAM, and In-System Programming (ISP) code.
8. The apparatus of claim 7 , wherein the interface comprises a plurality of channels, each channel is connected to a DRAM module and a PCM or magnetoresistive module, the DRAM modules of different channels are enabled by a first signal, and the PCM or magnetoresistive modules of different channels are enabled by a second signal.
9. The apparatus of claim 8 , wherein the processing unit is arranged to operably configure the interface in an operating mode for accessing data of the DRAM module before enabling the DRAM module by the first signal; and configure the interface in an operating mode for accessing data of the PCM or magnetoresistive module before enabling the PCM or magnetoresistive module by the second signal.
10. The apparatus of claim 7 , wherein the interface comprises a first channel and a second channel, the first channel is connected to a DRAM module only, and the second channel is connected to a PCM or magnetoresistive module only.
11. The apparatus of claim 10 , wherein the processing unit comprises a first core and a second core, the first core is arranged to operably control the first channel and the second core is arranged to operably control the second channel.
12. The apparatus of claim 1 , wherein the processing unit is arranged to operably detect types of all storage units connected thereto through an interface for finding the hybrid memory before initializing the hybrid memory.
13. The apparatus of claim 12 , wherein the processing unit is arranged to operably determine whether an enabled storage unit belongs to the hybrid memory by detecting a voltage level of a specific pin of the enabled storage unit through hardware of the interface.
14. The apparatus of claim 12 , wherein the processing unit is arranged to operably issue a command that can be recognized by the hybrid memory to an enabled storage unit, and determine whether the enabled storage unit belongs to the hybrid memory according to a reception of a correct or incorrect reply.
15. The apparatus of claim 12 , wherein the processing unit is arranged to operably read a second parameter for configuring a Dynamic Random Access Memory (DRAM) from the hybrid memory; and configure the DRAM according to the second parameter.
16. The apparatus of claim 12 , wherein the processing unit is arranged to operably request the host for allocating a portion of Dynamic Random Access Memory (DRAM) space of a host-side as a Host Memory Buffer (HMB).
17. A method for controlling different types of storage units, performed by a processing unit when loading and executing software or firmware instructions, comprising:
during a system booting stage, initializing a non-volatile hybrid memory;
reading a first parameter for configuring a flash memory, and an In-System Programming (ISP) code from the hybrid memory;
initializing the flash memory according to the first parameter; and
executing the ISP code to enter a normal mode and wait for a command issued by a host.
18. The method of claim 17 , comprising:
detecting types of all storage units connected thereto through an interface for finding the hybrid memory before initializing the hybrid memory.
19. The method of claim 18 , wherein the processing unit is arranged to operably determine whether an enabled storage unit belongs to the hybrid memory by detecting a voltage level of a specific pin of the enabled storage unit through hardware of the interface.
20. The method of claim 18 , wherein the processing unit is arranged to operably issue a command that can be recognized by the hybrid memory to an enabled storage unit, and determine whether the enabled storage unit belongs to the hybrid memory according to a reception of a correct or incorrect reply.
21. The method of claim 18 , comprising:
reading a second parameter for configuring a Dynamic Random Access Memory (DRAM) from the hybrid memory; and
configuring the DRAM according to the second parameter.
22. The method of claim 18 , comprising:
requesting the host for allocating a portion of Dynamic Random Access Memory (DRAM) space of a host-side as a Host Memory Buffer (HMB).