IP Library Granted Patent US 11,200,092
Granted Patent B2
US 11,200,092 · App. 16/888,918 · Granted Dec 14, 2021

Convolutional computing accelerator, convolutional computing method, and computer-readable storage medium

Inventors: Bo Zhang (Shenzhen, CN); Xiaoyu Yu (Shenzhen, CN); Yuwei Wang (Shenzhen, CN); Lixin Zhang (Shenzhen, CN)
Assignee: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED
G06F9/5027G06F1/08G06F9/3802G06F17/153G06N3/063
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Quick Facts
Patent No.
US 11,200,092
App. No.
16/888,918
Granted
Dec 14, 2021
Kind
B2
Abstract

Embodiments of this application relate to a convolutional computing accelerator, a convolutional computing method, and a convolutional computing device, which belong to the technical field of electronic circuits. The convolutional computing accelerator includes: a controller, a computing matrix, and a first cache. The computing matrix comprising at least one row of computing units, each row of computing units comprising at least two adjacent connected computing units. The controller is configured to control input data of each row of computing units to be loaded into the first cache, and to control the input data loaded into the first cache to be inputted into the two adjacent computing units in a corresponding row. Each of the computing units in the corresponding row is configured to perform, in a first clock cycle, a convolutional computation based on received input data and a pre-stored convolutional kernel.

Claims (38)

1. A convolutional computing accelerator, comprising: a controller, a computing matrix, and a first cache,

the computing matrix comprising at least one row of computing units, the at least one row of computing units comprising at least two computing units, wherein each of the at least two computing units is configured to receive input data in a first clock cycle, wherein the each of the at least two computing units pre-stores at least two convolutional kernels, and wherein a duration of the first clock cycle is not shorter than a sum of durations of second clock cycles, each of the at least two convolutional kernels corresponding to one of the second clock cycles, and the each of the at least two computing units is configured to perform convolutional computation based on the input data and the at least two convolutional kernels during one of the second clock cycles;

the controller being configured to control loading of the input data into the first cache, and to control the input data loaded into the first cache to be inputted into the at least two computing units, wherein the controller is configured to input the input data into a register of a first computing unit during the first clock cycle; and

each of the at least two computing units being configured to perform, in the first clock cycle, the convolutional computation based on the input data and the pre-stored convolutional kernel, wherein the first computing unit is configured to input the input data into a register of a next computing unit in the at least one row of computing units during a next first clock cycle, the first computing unit being a computing unit that is not a last computing unit in the at least one row of computing units.

2. The convolutional computing accelerator according to claim 1 , wherein

the convolutional computing accelerator further comprises a second cache, and the computing matrix comprises at least two rows of computing units, the at least two rows of computing units forming at least two columns, and two adjacent computing units in each column being connected; and

a second computing unit in the computing matrix is configured to store an accumulated convolutional computation result to the second cache.

3. The convolutional computing accelerator according to claim 2 , wherein the second computing unit is further configured to add a convolutional computation result obtained by performing a convolutional computation in a previous first clock cycle and a convolutional computation result transmitted by a previous computing unit in the previous first clock cycle, to obtain the accumulated convolutional computation result.

4. The convolutional computing accelerator according to claim 3 , wherein a third computing unit in the computing matrix is configured to:

output the convolutional computation result obtained by performing the convolutional computation in the previous first clock cycle to a next computing unit.

5. The convolutional computing accelerator according to claim 4 , wherein

the third computing unit is further configured to add the convolutional computation result to initial accumulated data to acquire an addition computation result; and

the third computing unit is further configured to output the addition computation result as an updated convolutional computation result.

6. The convolutional computing accelerator according to claim 3 , wherein a fourth computing unit in the computing matrix is configured to:

add the convolutional computation result, to obtain an addition computation result; and

output the addition computation result, as an updated convolutional computation result.

7. A convolutional computing method performed by a convolutional computing accelerator, the convolutional computing accelerator comprising: a controller, a computing matrix, and a first cache,

the computing matrix comprising at least one row of computing units, the at least one row of computing units comprising at least two computing units, wherein each of the at least two computing units is configured to receive input data in a first clock cycle, wherein the each of the at least two computing units pre-stores at least two convolutional kernels, and wherein a duration of the first clock cycle is not shorter than a sum of durations of second clock cycles, each of the at least two convolutional kernels corresponding to one of the second clock cycles, and the each of the at least two computing units is configured to perform convolutional computation based on the input data and the at least two convolutional kernels during one of the second clock cycles; the method comprising:

controlling, by the controller, loading of the input data into the first cache;

controlling, by the controller, the input data loaded into the first cache to be inputted into the at least two computing units, wherein the controller is configured to input the input data into a register of a first computing unit during the first clock cycle; and

performing, in the first clock cycle, by each of the at least two computing units, the convolutional computation based on the input data and the pre-stored convolutional kernel, wherein the first computing unit is configured to input the input data into a register of a next computing unit in the at least one row of computing units during a next first clock cycle, the first computing unit being a computing unit that is not a last computing unit in the at least one row of computing units.

8. The method according to claim 7 , wherein

the convolutional computing accelerator further comprises a second cache, the computing matrix comprising at least two rows of computing units, the at least two rows of computing units forming at least two columns, and two adjacent computing units in each column being connected; and

a second computing unit in the computing matrix is configured to add a convolutional computation result obtained by performing the convolutional computation in a previous first clock cycle and a convolutional computation result transmitted by a previous computing unit in a previous first clock cycle, to obtain an accumulated convolutional computation result, and to store the accumulated convolutional computation result to the second cache.

9. The method according to claim 8 , wherein a third computing unit in the computing matrix is configured to

output the convolutional computation result obtained by performing the convolutional computation in the previous first clock cycle to a next computing unit.

10. The method according to claim 8 , wherein a fourth computing unit in the computing matrix is configured to add the convolutional computation result, to obtain an addition computation result; and

output the addition computation result, as an updated convolutional computation result.

11. A non-transitory computer-readable storage medium, the storage medium storing one or computer executable instructions, when executed by one or more coprocessors, the computer executable instructions implement a method performed by a convolutional computing accelerator, the convolutional computing accelerator comprising: a controller, a computing matrix, and a first cache, the computing matrix comprising at least one row of computing units, the at least one row of computing units comprising at least two computing units, wherein each of the at least two computing units is configured to receive input data in a first clock cycle, wherein the each of the at least two computing units pre-stores at least two convolutional kernels, and wherein a duration of the first clock cycle is not shorter than a sum of durations of second clock cycles, each of the at least two convolutional kernels corresponding to one of the second clock cycles, and the each of the at least two computing units is configured to perform convolutional computation based on the input data and the at least two convolutional kernels during one of the second clock cycles; the method comprising:

controlling, by the controller, loading of the input data into the first cache;

controlling, by the controller, the input data loaded into the first cache to be inputted into the at least two connected computing units, wherein the controller is configured to input the input data into a register of a first computing unit during the first clock cycle; and

performing, in the first clock cycle, by each of the at least two computing units, the convolutional computation based on the input data and the pre-stored convolutional kernel, wherein the first computing unit is configured to input the input data into a register of a next computing unit in the at least one row of computing units during a next first clock cycle, the first computing unit being a computing unit that is not a last computing unit in the at least one row of computing units.

12. The non-transitory computer-readable storage medium according to claim 11 , wherein

the convolutional computing accelerator further comprises a second cache, the computing matrix comprising at least two rows of computing units, the at least two rows of computing units forming at least two columns, and two adjacent computing units in each column being connected; and

a second computing unit in the computing matrix is configured to add a convolutional computation result obtained by performing the convolutional computation in a previous first clock cycle and a convolutional computation result transmitted by a previous computing unit in a previous first clock cycle, to obtain an accumulated convolutional computation result, and to store the accumulated convolutional computation result to the second cache.

13. The non-transitory computer-readable storage medium according to claim 12 , wherein a third computing unit in the computing matrix is configured to output the convolutional computation result obtained by performing the convolutional computation in the previous first clock cycle to a next computing unit.

14. The non-transitory computer-readable storage medium according to claim 12 , wherein a fourth computing unit in the computing matrix is configured to add the convolutional computation result, to obtain an addition computation result; and

output the addition computation result, as an updated convolutional computation result.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 1, 2020
From: ZHANG, BO; YU, XIAOYU; WANG, YUWEI; ZHANG, LIXIN
To: TENCENT TECHNOLOGY (SHENZHEN) COMPANY LIMITED
Reel/Frame 052799/0284 →
Priority Claims (1)
CN 201810259875.1 · Mar 27, 2018 · national
Continuity (2)
Continuation PCTCN2019075431 · Feb 19, 2019
Related Publication 20200293379A1 · Sep 17, 2020
Cited By (1)
US 12,361,571