IP Library › Granted Patent US 11,205,003
Granted Patent B2
US 11,205,003 · App. 16/832,138 · Granted Dec 21, 2021

Platform security mechanism

Inventors: Baiju Patel (Portland, OR); Prashant Dewan (Portland, OR)
Assignee: Intel Corporation
G06F21/575G06F9/4413G06F21/602H04L9/0861H04L9/14H04L9/3278G06F2221/034
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Quick Facts
Patent No.
US 11,205,003
App. No.
16/832,138
Granted
Dec 21, 2021
Kind
B2
Abstract

An apparatus to facilitate security within a computing system is disclosed. The apparatus includes a storage drive, a controller, comprising a trusted port having one or more key slots to program one or more cryptographic keys and an encryption engine to receive the cryptographic keys via the one or more key slots, encrypt data written to the storage drive using the cryptographic keys and decrypt data read from the storage drive using the cryptographic keys.

Claims (45)

1. An apparatus to facilitate security within a computing system, comprising:

a non-volatile memory, including:

a storage drive;

a controller, comprising a trusted port having one or more key slots to program one or more cryptographic keys;

an encryption engine to receive the cryptographic keys via the one or more key slots, encrypt data written to the storage drive using the cryptographic keys and decrypt data read from the storage drive using the cryptographic keys; and

non-volatile memory further comprises Basic Input/Output System (BIOS) firmware to provision an operating system image into the non-volatile memory during a booting process,

wherein the BIOS firmware reads a security header included in the operating system image that provides an indication of storage blocks in the storage drive storing the operating system image as plain text and configures the controller to not decrypt storage blocks in the storage device indicated in the security header.

2. The apparatus of claim 1 , wherein the one or more cryptographic keys are programmed into the controller during manufacture of the non-volatile memory.

3. The apparatus of claim 2 , further comprising a security controller to generate the cryptographic keys.

4. The apparatus of claim 3 , wherein the security controller receives the cryptographic keys from a physically unclonable function (PUF) engine.

5. The apparatus of claim 3 , wherein the security controller receives the cryptographic keys from a fuse controller.

6. The apparatus of claim 1 , wherein the BIOS reads the operating system image from the storage blocks.

7. The apparatus of claim 6 , wherein the controller encrypts the operating system image via the cryptographic keys and stores the encrypted operating system image to the storage drive.

8. A method to facilitate security of a non-volatile memory, comprising:

receiving a write request to write data to the non-volatile memory;

encrypting the write data at an encryption engine included in the non-volatile memory via one or more cryptographic keys;

storing the encrypted write data at a storage drive within the non-volatile memory, and

provisioning, via Basic Input/Output System (BIOS) firmware, an operating system image into the non-volatile memory during a booting process, including:

reading a security header included in the operating system image that provides an indication of storage blocks in the storage drive storing the operating system image as plain text; and

configuring the controller to not decrypt storage blocks in the storage device indicated in the security header.

9. The method of claim 8 , further comprising:

receiving a read request to read data from the non-volatile memory;

retrieving encrypted data from the storage drive within the non-volatile memory; and

decrypting the data at the encryption engine via the one or more cryptographic keys.

10. The method of claim 9 , further comprising transmitting the data.

11. The method of claim 8 further comprising the BIOS reading the operating system image from the storage blocks.

12. The method of claim 11 , further comprising:

encrypting the operating system image via the cryptographic keys; and

storing the encrypted operating system image to the storage drive.

13. A computing device comprising:

a processor;

a memory device;

a fabric interface coupled between the processor and the memory device; and

a non-volatile memory, coupled to the fabric interface, including:

a storage drive;

a controller comprising a trusted port having one or more key slots to program one or more cryptographic keys;

an encryption engine to receive the cryptographic keys via the one or more key slots, encrypt data written to the storage drive using the cryptographic keys and decrypt data read from the storage drive using the cryptographic keys; and

non-volatile memory further comprises Basic Input/Output System (BIOS) firmware to provision an operating system image into the non-volatile memory during a booting process,

wherein the BIOS firmware reads a security header included in the operating system image that provides an indication of storage blocks in the storage drive storing the operating system image as plain text and configures the controller to not decrypt storage blocks in the storage device indicated in the security header.

14. The computing device of claim 13 , wherein the one or more cryptographic keys are programmed into the controller during manufacture of the non-volatile memory.

15. The computing device of claim 14 , further comprising a security controller, coupled to the fabric interface, to generate the cryptographic keys.

16. The computing device of claim 15 , wherein the security controller receives the cryptographic keys from a physically unclonable function (PUF) engine.

17. The computing device of claim 15 , wherein the security controller receives the cryptographic keys from a fuse controller.

18. The computing device of claim 13 , wherein the BIOS reads the operating system image from the storage blocks.

19. The computing device of claim 18 , wherein the controller encrypts the operating system image via the cryptographic keys and stores the encrypted operating system image to the storage drive.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 8, 2020
From: PATEL, BAIJU; DEWAN, PRASHANT
To: INTEL CORPORATION
Reel/Frame 053147/0265 →
Continuity (1)
Related Publication 20200226263A1 · Jul 16, 2020
Cited By (5)
US 12,455,701 US 12,487,762 US 12,518,026 US 12,541,416 US 12,717,744