IP Library Granted Patent US 11,205,619
Granted Patent B2
US 11,205,619 · App. 16/924,042 · Granted Dec 21, 2021

Hybrid bonding using dummy bonding contacts and dummy interconnects

Inventors: Tao Wang (Wuhan, CN); Si Ping Hu (Wuhan, CN); Jia Wen Wang (Wuhan, CN); Shi Qi Huang (Wuhan, CN); Jifeng Zhu (Wuhan, CN); Jun Chen (Wuhan, CN); Zi Qun Hua (Wuhan, CN)
Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
H01L23/53238H01L21/76841H01L23/5384H01L24/06H01L24/19H01L24/20H01L27/1157H01L27/11582
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Quick Facts
Patent No.
US 11,205,619
App. No.
16/924,042
Granted
Dec 21, 2021
Kind
B2
Abstract

Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a semiconductor device includes a first and a second semiconductor structures. The first semiconductor structure includes a first interconnect layer including first interconnects. At least one first interconnect is a first dummy interconnect. The first semiconductor structure further includes a first bonding layer including first bonding contacts. Each first interconnect is in contact with a respective first bonding contact. The second semiconductor structure includes a second interconnect layer including second interconnects. At least one second interconnect is a second dummy interconnect. The second semiconductor structure further includes a second bonding layer including second bonding contacts. Each second interconnect is in contact with a respective second bonding contact. The semiconductor device further includes a bonding interface between the first and second bonding layers. Each first bonding contact is in contact with a respective second bonding contact at the bonding interface.

Claims (23)

1. A method for forming a semiconductor device, comprising:

forming a first interconnect layer comprising a plurality of first interconnects above a first substrate, wherein at least one of the first interconnects is at least one first dummy interconnect;

forming a first bonding layer comprising a plurality of first bonding contacts above the first interconnect layer, such that each of the first interconnects is in contact with a respective one of the first bonding contacts;

forming a second interconnect layer comprising a plurality of second interconnects above a second substrate, wherein at least one of the second interconnects is at least one second dummy interconnect;

forming a second bonding layer comprising a plurality of second bonding contacts above the second interconnect layer, such that each of the second interconnects is in contact with a respective one of the second bonding contacts; and

bonding the first substrate and the second substrate in a face-to-face manner, such that each of the first bonding contacts is in contact with a respective one of the second bonding contacts at a bonding interface.

2. The method of claim 1 , wherein forming the first bonding layer comprises forming the first bonding contacts by a single patterning process.

3. The method of claim 1 , wherein forming the second bonding layer comprises forming the second bonding contacts by a single patterning process.

4. The method of claim 1 , wherein a number of the first bonding contacts is the same as a number of first interconnects, and a number of the first bonding contacts is the same as a number of first interconnects.

5. The method of claim 1 , wherein each of the first bonding contacts has a nominally same first critical dimension, and each of the second bonding contacts has a nominally same second critical dimension.

6. The method of claim 1 , wherein:

forming the first bonding layer comprises forming a first dielectric in the first bonding layer;

forming the second bonding layer comprises forming a second dielectric in the second bonding layer; and

the first dielectric is in contact with the second dielectric at the bonding interface after the bonding.

7. The method of claim 1 , further comprising:

forming a first device layer having a NAND memory string between the first interconnect layer and the first substrate; and

forming a second device layer having a peripheral device between the second interconnect layer and the second substrate,

wherein the first and second dummy interconnects are not electrically connected to the NAND memory string and the peripheral device.

8. The method of claim 1 , further comprising:

forming a first device layer having a peripheral device between the first interconnect layer and the first substrate; and

forming a second device layer having a NAND memory string between the second interconnect layer and the second substrate,

wherein the first and second dummy interconnects are not electrically connected to the NAND memory string and the peripheral device.

9. The method of claim 1 , wherein the bonding comprises hybrid bonding.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 8, 2020
From: WANG, TAO; HU, SI PING; WANG, JIA WEN; HUANG, SHI QI; ZHU, JIFENG; CHEN, JUN; HUA, ZI QUN
To: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
Reel/Frame 053156/0377 →
Continuity (3)
Division 16292279 · Mar 4, 2019
Continuation PCTCN2019073909 · Jan 30, 2019
Related Publication 20200335450A1 · Oct 22, 2020
Cited By (1)
US 12,672,576