IP Library › Granted Patent US 11,210,186
Granted Patent B2
US 11,210,186 · App. 16/295,226 · Granted Dec 28, 2021

Error recovery storage for non-associative memory

Inventors: Peter Vrabel (Cambridge, GB); Alan Jeremy Becker (Bushey, GB)
Assignee: Arm Limited
G06F11/2017G06F11/1064G06F11/1435G06F12/0292G06F12/0897G06F12/0826
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Quick Facts
Patent No.
US 11,210,186
App. No.
16/295,226
Granted
Dec 28, 2021
Kind
B2
Abstract

An apparatus comprises a non-associative memory comprising a plurality of storage locations, and error recovery storage to store at least one error recovery entry providing a recovery value for a corresponding storage location of the non-associative memory. Control circuitry is responsive to a non-associative memory read request specifying a target address of a storage location of the non-associative memory, when the error recovery storage includes a valid matching error recovery entry for which the corresponding storage location is the storage location identified by the target address, to return the recovery value stored in the valid matching error recovery entry as a response to the non-associative memory read request, instead of information stored in the storage location identified by the target address. This enables the apparatus to continue to function even if hard errors occur in a storage location of the non-associative memory.

Claims (32)

1. An apparatus comprising:

a non-associative memory comprising a plurality of storage locations;

error recovery storage to store at least one error recovery entry providing a recovery value for a corresponding storage location of the non-associative memory; and

control circuitry responsive to a non-associative memory read request specifying a target address of a storage location of the non-associative memory, when the error recovery storage includes a valid matching error recovery entry for which the corresponding storage location is the storage location identified by the target address, to return the recovery value stored in said valid matching error recovery entry as a response to the non-associative memory read request, instead of information stored in the storage location identified by the target address,

in which each error recovery entry comprises a lock field indicative of whether the error recovery entry is allowed to be evicted from the error recovery storage by the control circuitry.

2. The apparatus according to claim 1 , in which in response to a non-associative memory write request specifying a write target address and a write value to be written to the storage location of the non-associative memory identified by the write target address, when the error recovery storage includes a valid matching error recovery entry for which the corresponding storage location is the storage location identified by the write target address, the control circuitry is configured to update at least a portion of the recovery value stored in the valid matching error recovery entry based on the write value specified by the non-associative memory write request.

3. The apparatus according to claim 2 , in which each error recovery entry comprises at least one poison field, each poison field indicative of whether a corresponding portion of the recovery value is usable as a response to the non-associative memory read request; and

in response to the non-associative memory write request, when a given poison field of the valid matching error recovery entry indicates that a given portion of the recovery value is unusable, and the non-associative memory write request requests overwriting of all bits within a portion of the storage location corresponding to said given portion of the recovery value, the control circuitry is configured to update said given portion of the recovery value based on the write value and to update the given poison field to indicate that said given portion of the recovery value is now usable.

4. The apparatus according to claim 2 , in which in response to the non-associative memory write request, when the error recovery storage includes a valid matching error recovery entry for which the corresponding storage location is the storage location identified by the write target address, the control circuitry is also configured to write the write value to the storage location of the non-associative memory identified by the write target address.

5. The apparatus according to claim 1 , comprising error detection circuitry to detect errors in information stored in the non-associative memory.

6. The apparatus according to claim 5 , in which in response to detection of an error in information stored in a given storage location of the non-associative memory, when the error detected by the error detection circuitry is correctable and the error recovery storage includes at least one error recovery entry that is updatable by the control circuitry, the control circuitry is configured to update the error recovery storage to provide a valid error recovery entry for which the corresponding storage location is the given storage location and the recovery value is an error-corrected value of the information stored in the given storage location.

7. The apparatus according to claim 5 , in which each error recovery entry comprises at least one poison field, each poison field indicative of whether a corresponding portion of the recovery value is usable as a response to the non-associative memory read request; and

in response to detection of an error in information stored in a given storage location of the non-associative memory, when the error detected by the error detection circuitry is uncorrectable, the control circuitry is configured to update the error recovery storage to provide a valid error recovery entry for which the corresponding storage location is the given storage location and the at least one poison field specifies that at least part of the recovery value is unusable.

8. The apparatus according to claim 1 , in which the lock field of a given error recovery entry is restricted to being updated by software executed by processing circuitry of the apparatus.

9. The apparatus according to claim 1 , in which the non-associative memory comprises a tightly coupled memory.

10. The apparatus according to claim 1 , in which the non-associative memory comprises a direct-mapped cache.

11. The apparatus according to claim 1 , in which each error recovery entry comprises a validity field and an address field; and

the valid matching error recovery entry comprises an error recovery entry for which the validity field indicates that the error recovery entry is valid and the address field indicates an address matching the target address.

12. An apparatus comprising:

a non-associative memory comprising a plurality of storage locations;

error recovery storage to store at least one error recovery entry providing a recovery value for a corresponding storage location of the non-associative memory; and

control circuitry responsive to a non-associative memory read request specifying a target address of a storage location of the non-associative memory, when the error recovery storage includes a valid matching error recovery entry for which the corresponding storage location is the storage location identified by the target address, to return the recovery value stored in said valid matching error recovery entry as a response to the non-associative memory read request, instead of information stored in the storage location identified by the target address, in which

each error recovery entry comprises at least one poison field, each poison field indicative of whether a corresponding portion of the recovery value is usable as a response to the non-associative memory read request.

13. The apparatus according to claim 12 , in which the error recovery entry comprises a single poison field for which the corresponding portion comprises the entire recovery value.

14. The apparatus according to claim 12 , in which the error recovery entry comprises a plurality of poison fields corresponding to respective portions of the recovery value.

15. The apparatus according to claim 12 , in which, in response to the non-associative memory read request, when the at least one poison field of the valid matching error recovery entry indicates that one or more required portions of the recovery value required for responding to the non-associative memory read request are all usable, the control circuitry is configured to return said one or more required portions of the recovery value as the response to the non-associative memory read request.

16. The apparatus according to claim 12 , in which, in response to the non-associative memory read request, when the at least one poison field of the valid matching error recovery entry indicates that at least one required portion of the recovery value required for responding to the non-associative memory read request is unusable, the control circuitry is configured to return an error indication.

17. A method for controlling access to a non-associative memory comprising a plurality of storage locations; comprising:

receiving a non-associative memory read request specifying a target address of a storage location of the non-associative memory;

looking up the target address in error recovery storage comprising at least one error recovery entry providing a recovery value for a corresponding storage location of the non-associative memory; and

when the error recovery storage includes a valid matching error recovery entry for which the corresponding storage location is the storage location identified by the target address, returning the recovery value stored in said valid matching error recovery entry as a response to the non-associative memory read request, instead of information stored in the storage location identified by the target address,

in which each error recovery entry comprises at least one poison field, each poison field indicative of whether a corresponding portion of the recovery value is usable as a response to the non-associative memory read request.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 7, 2019
From: VRABEL, PETER; BECKER, ALAN JEREMY
To: ARM LIMITED
Reel/Frame 050111/0539 →
Continuity (1)
Related Publication 20200285550A1 · Sep 10, 2020