IP Library › Granted Patent US 11,210,244
Granted Patent B2
US 11,210,244 · App. 16/843,871 · Granted Dec 28, 2021

Local internal discovery and configuration of individually selected and jointly selected devices

Inventor: John Eric Linstadt (Palo Alto, CA)
Assignee: Rambus Inc.
G06F13/1694G06F12/0246G06F12/0623G06F12/0646G11C7/10G11C7/1045G11C7/20G11C7/22G06F13/1678G06F2212/7206
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 11,210,244
App. No.
16/843,871
Granted
Dec 28, 2021
Kind
B2
Abstract

A memory controller interfaces with one or more memory devices having configurable width data buses and configurable connectivity between data pins of the memory devices and data pins of the memory controller. Upon initialization of the memory devices, the memory controller automatically discovers the connectivity configuration of the one or more memory devices, including both individually selected and jointly selected devices. After discovering connectivity of the connected devices, the memory controller configures the memory devices according to the discovered connectivity and assigns unique addresses to jointly selected devices.

Claims (40)

1. A configurable width device, comprising:

a multiplexer coupled to a plurality of data lines, the multiplexer selectively associating one or more of the plurality of data lines with one or more of a plurality of data pins; and

device logic to receive a connectivity read command from a controller during an initialization sequence and output a plurality of bit patterns including a plurality of bits to the plurality of data pins responsive to the connectivity read command, each of the bit patterns having a single bit representing a first logic state that is predetermined and remaining bits representing a second logic state, and each of the bit patterns having a different one of the plurality of bits in the first logic state relative to remaining ones of the bit patterns.

2. The configurable width device of claim 1 , further comprising:

a pre-programmed register to store the one or more bit patterns and to output the one or more bit patterns to the plurality of data pins responsive to the connectivity read command.

3. The configurable width device of claim 2 , wherein the pre-programmed register comprises a non-volatile register.

4. The configurable width device of claim 1 , wherein the device logic receives the one or more bit patterns from the controller with the connectivity read command and wherein the configurable width device echoes the one or more bit patterns responsive to the connectivity read command.

5. The configurable width device of claim 1 , wherein the device logic outputs the plurality of bit patterns in a sequence, wherein each subsequent bit pattern in the sequence has a bit in the first logic state moved by one bit position relative to a prior bit pattern in the sequence.

6. The configurable width device of claim 1 , wherein the device logic further receives a connectivity write command and configures the multiplexer to map the one or more of the plurality of data lines to the one or more of the plurality of data pins based on the connectivity write command.

7. The configurable width device of claim 1 , wherein the multiplexer is configured to provide a one-to-one mapping between the plurality of data lines and the plurality of data pins.

8. The configurable width device of claim 1 , wherein the multiplexer is configured to map two or more of the plurality of data lines to a common data pin.

9. The configurable width device of claim 1 , wherein the device logic is further configured to:

receive a connectivity echo command including one or more echoed bit patterns and store the one or more echoed bit patterns;

apply a rotation to the one or more echoed bit patterns to generate one or more rotated bit patterns each corresponding to one of the echoed bit patterns, each of the rotated bit patterns having at least some of the bits at different bit positions compared to the corresponding one of the echoed bit pattern; and

output the rotated bit patterns to the plurality of data pins.

10. A method for operating a configurable width device comprising:

selectively associating, by a multiplexer coupled to a plurality of data lines, one or more of the plurality of data lines with one or more of a plurality of data pins;

receiving, by device logic, a connectivity read command from a controller during an initialization sequence;

outputting, by the device logic, a plurality of bit patterns to the plurality of data pins responsive to the connectivity read command, each of the bit patterns having a single bit representing a first logic state that is predetermined and remaining bits representing a second logic state, and each of the bit patterns having a different one of the plurality of bits in the first logic state relative to remaining ones of the bit patterns.

11. The method of claim 10 , wherein outputting the plurality of bit patterns comprises:

reading the plurality of bit patterns from a pre-programmed register.

12. The method of claim 10 , wherein outputting the plurality of bit patterns comprises:

receiving the plurality of bit patterns from the controller with the connectivity read command; and

echoing the plurality of bit patterns.

13. The method of claim 10 , wherein outputting the plurality of bit patterns comprises:

outputting the plurality of bit patterns in a sequence, wherein each subsequent bit pattern in the sequence has a bit in the first logic state moved by one bit position relative to a prior bit pattern in the sequence.

14. The method of claim 10 , further comprising:

receiving, by the device logic, a connectivity write command after outputting the plurality of bit patterns; and

configuring the multiplexer to map the one or more of the plurality of data lines to the one or more of the plurality of data pins based on the connectivity write command.

15. The method of claim 14 , further comprising:

receiving a second connectivity read command following the connectivity write command; and

re-outputting the plurality of bit patterns following the second connectivity read command.

16. The method of claim 10 , wherein selectively associating the one or more of the plurality of data lines with the one or more of the plurality of data pins comprises:

associating, by the multiplexer, the plurality of data lines and the plurality of data pins according to a one-to-one mapping.

17. The method of claim 10 , wherein selectively associating the one or more of the plurality of data lines with the one or more of the plurality of data pins comprises:

associating, by the multiplexer, two or more of the plurality of data lines to a common data pin.

18. The method of claim 10 , further comprising:

receiving, by the device logic, a connectivity echo command including one or more echoed bit patterns and store the one or more echoed bit patterns to a register;

applying, by the device logic, a rotation to the one or more echoed bit patterns to generate one or more rotated bit patterns each corresponding to one of the echoed bit patterns, each of the rotated bit patterns having at least some of the bits at different bit positions compared to the corresponding one of the echoed bit pattern; and

outputting, by the device logic, the rotated bit patterns to the plurality of data pins.

Continuity (5)
Continuation 16243055 · Jan 8, 2019
Continuation 15867646 · Jan 10, 2018
Continuation 14438865
Provisional Application 61734203 · Dec 6, 2012
Related Publication 20200293471A1 · Sep 17, 2020