Imaging device and electronic apparatus
An imaging device includes a plurality of pixel transistors at a substrate surface of a semiconductor substrate, an element isolation region that isolates the plurality of pixel transistors from each other, a charge storage region at a deeper position in the semiconductor substrate than the substrate surface, and a charge discharge layer of the same conductivity type as the charge storage region. The charge discharge layer is arranged between the element isolation region and the charge storage region.
1. An imaging device, comprising:
a plurality of pixel transistors at a surface of a semiconductor substrate;
an element isolation region that isolates the plurality of pixel transistors from each other;
a charge storage region at a deeper position in the semiconductor substrate than a substrate surface; and
a charge discharge layer of the same conductivity type as the charge storage region,
wherein the charge discharge layer is arranged between the element isolation region and the charge storage region,
wherein the charge discharge layer is coupled to an impurity region having a same conductivity type as the charge storage region,
wherein the impurity region is at the substrate surface, and
wherein the impurity region is a drain region of at least one of a reset transistor or an amplification transistor of the plurality of pixel transistors.
2. The imaging device according to claim 1 , wherein the charge discharge layer is arranged below the element isolation region.
3. The imaging device according to claim 1 , wherein the charge discharge layer is in a well region between the element isolation region and the charge storage region.
4. The imaging device according to claim 1 , wherein the charge discharge layer is between the charge storage region and at least one of the plurality of pixel transistors that is not a transfer transistor.
5. The imaging device according to claim 1 , wherein the charge discharge layer includes an opening, and a gate electrode of a transfer transistor in the plurality of pixel transistors extends through the opening into the charge storage region.
6. The imaging device according to claim 1 , wherein a transfer transistor of the plurality of pixel transistors has a trench structure in which a gate electrode extends from the substrate surface to the charge storage region.
7. The imaging device according to claim 1 , further comprising:
an inter-pixel isolation section configured to penetrate the semiconductor substrate, the inter-pixel isolation section being arranged in a pixel boundary outside the charge storage region in a planar view.
8. The imaging device according to claim 1 , further comprising:
a light-shielding film and an on-chip lens on a side of another surface of the semiconductor substrate that is different from a surface of the substrate surface.
9. An electronic apparatus, comprising an imaging device as defined in claim 1 .
10. An imaging device, comprising:
a plurality of pixel transistors at a surface of a semiconductor substrate;
an element isolation region that isolates the plurality of pixel transistors from each other;
a charge storage region at a deeper position in the semiconductor substrate than a substrate surface; and
a charge discharge layer of the same conductivity type as the charge storage region,
wherein the charge discharge layer is arranged between the element isolation region and the charge storage region,
wherein the charge discharge layer is coupled to an impurity region having a same conductivity type as the charge storage region,
wherein the impurity region is at the substrate surface, and
wherein the impurity region is a drain region of an amplification transistor of the plurality of pixel transistors.
11. The imaging device according to claim 10 , wherein the charge discharge layer is arranged below the element isolation region.
12. The imaging device according to claim 10 , wherein the charge discharge layer is in a well region between the element isolation region and the charge storage region.
13. The imaging device according to claim 10 , wherein the charge discharge layer is between the charge storage region and at least one of the plurality of pixel transistors that is not a transfer transistor.
14. An imaging device, comprising:
a plurality of pixel transistors at a surface of a semiconductor substrate;
an element isolation region that isolates the plurality of pixel transistors from each other;
a charge storage region at a deeper position in the semiconductor substrate than a substrate surface; and
a charge discharge layer of the same conductivity type as the charge storage region,
wherein the charge discharge layer is arranged between the element isolation region and the charge storage region,
wherein the charge discharge layer is coupled to an impurity region having a same conductivity type as the charge storage region,
wherein the impurity region is at the substrate surface, and
wherein the impurity region receives a predetermined voltage (VDD).
15. An imaging device, comprising:
a plurality of pixel transistors at a surface of a semiconductor substrate;
an element isolation region that isolates the plurality of pixel transistors from each other;
a charge storage region at a deeper position in the semiconductor substrate than a substrate surface; and
a charge discharge layer of the same conductivity type as the charge storage region,
wherein the charge discharge layer is arranged between the element isolation region and the charge storage region,
wherein the charge discharge layer is coupled to an impurity region having a same conductivity type as the charge storage region,
wherein the impurity region is at the substrate surface, and
wherein the impurity region is between an amplification transistor and a selection transistor of the plurality of pixel transistors.
16. An imaging device, comprising:
a plurality of pixel transistors at a surface of a semiconductor substrate;
an element isolation region that isolates the plurality of pixel transistors from each other;
a charge storage region at a deeper position in the semiconductor substrate than a substrate surface;
a charge discharge layer of the same conductivity type as the charge storage region; and
an inter-pixel isolation section configured to penetrate the semiconductor substrate,
wherein the inter-pixel isolation section is arranged in a pixel boundary outside the charge storage region in a planar view,
wherein the charge discharge layer is arranged between the element isolation region and the charge storage region, and
wherein the inter-pixel isolation section includes a double-layer structure of a sidewall film and a filler inside the double-layer structure of the sidewall film.
17. The imaging device according to claim 16 , wherein the charge discharge layer is coupled to an impurity region having a same conductivity type as the charge storage region, wherein the impurity region is at the substrate surface.
18. The imaging device according to claim 16 , wherein the impurity region is separate from a source region and a drain region of the plurality of pixel transistors.
19. An imaging device, comprising:
a plurality of pixel transistors at a surface of a semiconductor substrate;
an element isolation region that isolates the plurality of pixel transistors from each other;
a charge storage region at a deeper position in the semiconductor substrate than a substrate surface;
a charge discharge layer of the same conductivity type as the charge storage region, wherein the charge discharge layer is arranged between the element isolation region and the charge storage region;
an inter-pixel isolation section configured to penetrate the semiconductor substrate, wherein the inter-pixel isolation section is arranged in a pixel boundary outside the charge storage region in a planar view; and
a P-type layer and an N-type layer configured to form a PN junction, the P-type layer and the N-type layer being arranged between the charge storage region and the inter-pixel isolation section.
20. An imaging device, comprising:
a substrate;
a charge storage region in the substrate to store charge generated by incident light;
at least one transistor at a surface of the substrate and coupled to the charge storage region;
an isolation region in the substrate and located adjacent to at least one side of the at least one transistor; and
a charge discharge layer between the isolation region and the charge storage region, wherein the charge discharge layer discharges charge from the isolation region;
an impurity region in the substrate and coupled to the charge discharge layer, wherein the isolation region is between the impurity region and the at least one transistor,
wherein the impurity region, the charge storage region and the charge discharge layer have a same conductivity type, and
wherein the impurity region has a higher impurity concentration than the charge discharge layer.