Vertical intercalation device for neuromorphic computing
View Patent ↗Vertically stacked memory devices and methods of manufacture are provided. The structures include a substrate stack including a first row of horizontal electrodes disposed over a first insulating layer and first insulating layer disposed over a substrate. The substrate stack further includes a second row of horizontal electrodes separated from the first row of horizontal electrodes by a second insulating layer, and the first row of horizontal electrodes is form over and substantially parallel to the second row of horizontal electrodes. A third insulating layer is formed over the second row of horizontal electrodes. A plurality of vertical gate trenches formed through the third insulating layer, the second row of horizontal electrodes, the second insulating layer, the first row of horizontal electrodes and the first insulating layer. The plurality of vertical gate trenches filled with a layer of channel material, a layer of electrolyte material and filled with a metal.
1. A method for fabricating a vertically stacked memory device, the method comprising:
forming a stack by
depositing a second electronic insulating layer over a first ionic layer, the first ionic layer disposed over a first electronic insulating layer, and the first electronic insulating layer disposed over a substrate;
depositing a first electrode layer;
patterning the first electrode layer into a first row of horizontal electrodes over the second electronic insulating layer, wherein the first row of horizontal electrodes is formed of titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), or a combination thereof;
depositing a fourth electronic insulating layer over a second ionic layer, the second ionic layer disposed over a third electronic insulating layer, the third electronic insulating layer disposed over the first row of horizontal electrodes;
depositing a second electrode layer;
patterning the second electrode layer into a second row of horizontal electrodes over the fourth electronic insulating layer, wherein the second row of horizontal electrodes is formed of titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), or a combination thereof;
depositing a sixth electronic insulating layer over a third ionic layer disposed over a fifth electronic insulating layer disposed over the second row of horizontal electrodes;
forming a set of vertical gate trenches in the stack;
conformally depositing a layer of channel material in the set of vertical gate trenches;
conformally depositing a layer of electrolyte material in contact with the layer of channel material, wherein the layer of electrolyte material comprises one of lithium ion, hydrogen ion, and oxygen ion, which is intercalated in a tungsten trioxide (WO 3 ) of the layer of channel material; and
filling the set of vertical gate trenches with a metal to form a vertical gate electrode on top of the layer of electrolyte material.
2. The method of claim 1 , further comprising:
removing, by planarizing, the metal, the layer of channel material, and the layer of electrolyte material formed above the set of vertical gate trenches; and
depositing a dielectric layer to encapsulate the electrolyte material inside the set of vertical gate trenches.
3. The method of claim 1 , wherein the layer of electrolyte material forms part of the layer of channel material in an electrochemical random access memory (ECRAM).
4. The method of claim 1 ,
wherein one or more of the first electronic insulating layer and the second electronic insulating layer is formed of silicon nitride (SiN).
5. The method of claim 4 , wherein the third electronic insulating layer is formed of silicon nitride (SiN).
6. The method of claim 5 , wherein the fifth electronic insulating layer is formed of silicon nitride (SiN).
7. The method of claim 6 , wherein the sixth electronic insulating layer is formed of silicon nitride (SiN).
8. The method of claim 1 , wherein the first ionic layer or the second ionic layer is formed of silicon dioxide (SiO2), or both are formed of silicon dioxide (SiO2).
9. The method of claim 1 , wherein the third ionic layer is formed of silicon dioxide (SiO2).
10. The method of claim 1 , wherein the first ionic layer or the second ionic layer has a thickness from 10 nm to 100 nm, or both the first ionic layer and the second ionic layer have a thickness from 10 nm to 100 nm.
11. The method of claim 1 , wherein the third ionic layer has a thickness from 10 nm to 100 nm.
12. The method of claim 1 , wherein the first row of horizontal electrodes has a thickness from 10 nm to 100 nm.
13. The method of claim 1 , wherein the second row of horizontal electrodes has a thickness from 10 nm to 100 nm.
14. The method of claim 1 , wherein one or more of the first electronic insulating layer, the second electronic insulating layer, the third electronic insulating layer, the fourth electronic insulating layer, the first electronic insulating layer, and the sixth electronic insulating layer has a thickness from 1 nm to 10 nm.