IP Library › Granted Patent US 11,211,519
Granted Patent B2
US 11,211,519 · App. 17/000,226 · Granted Dec 28, 2021

Method for manufacturing solar cell

Inventors: Ryota Mishima (Osaka, JP); Kunihiro Nakano (Osaka, JP); Katsunori Konishi (Osaka, JP); Daisuke Adachi (Osaka, JP); Takashi Kuchiyama (Osaka, JP); Kenji Yamamoto (Osaka, JP)
Assignee: KANEKA CORPORATION
H01L31/202H01L31/02363H01L31/0747H01L31/1804
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Quick Facts
Patent No.
US 11,211,519
App. No.
17/000,226
Granted
Dec 28, 2021
Kind
B2
Abstract

The method for manufacturing a solar cell includes: forming a first semiconductor layer of first conductivity type on a surface of a semiconductor substrate; forming a lift-off layer containing a silicon-based material on the first semiconductor layer; selectively removing the lift-off layer and first semiconductor layer; forming a second semiconductor layer of second conductivity type on a surface having the lift-off layer and first semiconductor layer; and removing the second semiconductor layer covering the lift-off layer by removing the lift-off layer using an etching solution. The linear expansion coefficients of the semiconductor substrate and the lift-off layer satisfy the relational expression: the linear expansion coefficient of the lift-off layer <the linear expansion coefficient of the semiconductor substrate, and the forming of the second semiconductor layer or the removing of the second semiconductor layer is performed at a temperature higher than the temperature in the forming of the lift-off layer.

Claims (19)

1. A method for manufacturing a solar cell, the method comprising:

forming a first semiconductor layer of a first conductivity type on one of two major surfaces of a semiconductor substrate, the two major surfaces facing each other;

forming a first lift-off layer containing a silicon-based thin film material on the first semiconductor layer;

selectively removing the first lift-off layer and the first semiconductor layer;

forming a second semiconductor layer of a second conductivity type on the one major surface having the first lift-off layer and the first semiconductor layer; and

removing the second semiconductor layer covering the first lift-off layer by removing the first lift-off layer using an etching solution, wherein

linear expansion coefficients of the semiconductor substrate and the first lift-off layer satisfy the following relational expression (1):

the linear expansion coefficient of the first lift-off layer<the linear expansion coefficient of the semiconductor substrate . . . (1), and

at least one of the forming of the second semiconductor layer or the removing of the second semiconductor layer is performed at a processing temperature higher than a processing temperature in the forming of first the lift-off layer, wherein

the forming of the first semiconductor layer includes forming a first intrinsic semiconductor layer on the one major surface of the semiconductor substrate prior to the forming of the first semiconductor layer,

the selective removing of the first semiconductor layer includes selectively removing the first semiconductor layer and then the first intrinsic semiconductor layer,

the forming of the second semiconductor layer includes forming a second intrinsic semiconductor layer on the one major surface of the semiconductor substrate prior to the forming of the second semiconductor layer, the one major surface having a second lift-off layer, the first lift-off layer, and the first semiconductor layer, and

the removing of the second semiconductor layer includes selectively removing the second semiconductor layer and then the second intrinsic semiconductor layer.

2. The method of claim 1 , wherein

the first lift-off layer contains silicon oxide as a main component, and

in the selective removing of the first lift-off layer and the first semiconductor layer and the removing of the second semiconductor layer covering the first lift-off layer by removing the first lift-off layer using the etching solution, an etching rate for the first semiconductor layer and an etching rate for the first lift-off layer satisfy the following relational expression (2):

the etching rate for the first semiconductor layer≤the etching rate for the first lift-off layer . . . (2).

3. The method of claim 1 , wherein

a surface of the semiconductor substrate at least having the first semiconductor layer and the second semiconductor layer has a texture structure.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 21, 2020
From: MISHIMA, RYOTA; NAKANO, KUNIHIRO; KONISHI, KATSUNORI; ADACHI, DAISUKE; KUCHIYAMA, TAKASHI; YAMAMOTO, KENJI
To: KANEKA CORPORATION
Reel/Frame 053567/0593 →
Priority Claims (1)
JP JP2018-030758 · Feb 23, 2018 · national
Continuity (2)
Continuation PCTJP2019005407 · Feb 14, 2019
Related Publication 20200411713A1 · Dec 31, 2020