Memory system and operation method thereof
A memory system includes: a first error detection circuit suitable for generating a first error detection code using host data and a host address which are transferred from a host; a second error detection circuit suitable for generating a second error detection code using system data including one or more host data, a logical address corresponding to one or more host addresses, a physical address corresponding to the logical address and one or more first error detection codes; a third error detection code suitable for generating a third error detection code using the system data, the one or more first error detection codes and the second error detection code; and a first memory suitable for storing the system data, the one or more first error detection codes, the second error detection code and the third error detection code.
1. A memory system comprising:
a first error detection circuit configured to generate a first error detection code using host data and a host address which are transferred from a host;
a second error detection circuit configured to generate a second error detection code using system data including the host data, a logical address corresponding to the host address, a physical address corresponding to the logical address and the first error detection code;
a third error detection circuit configured to generate a third error detection code using the system data, the first error detection code and the second error detection code; and
a first memory configured to store the system data, the first error detection code, the second error detection code and the third error detection code.
2. The memory system of claim 1 , further comprising a second memory configured to store a mapping table between the logical address and the physical address.
3. The memory system of claim 1 , wherein the first error detection circuit generates the first error detection code by further using a poison bit,
the second error detection circuit generates the second error detection code by further using the poison bit,
the third error detection circuit generates the third error detection code by further using the poison bit, and
the first memory further stores the poison bit.
4. The memory system of claim 3 , wherein the second error detection circuit generates the second error detection code by further using meta data,
the third error detection circuit generates the third error detection code by further using the meta data, and
the first memory further stores the meta data.
5. The memory system of claim 1 , wherein the third error detection code comprises information for detecting errors of the system data, the first error detection code and the second error detection code and correcting the detected errors.
6. The memory system of claim 1 , wherein the first error detection code is a cyclic redundancy check (CRC) code,
the second error detection code is a CRC code, and
the third error detection code is a Reed-Solomon (RS) code.
7. The memory system of claim 1 , wherein the third error detection circuit detects errors of the system data, the first error detection code and the second error detection code, which are read from the first memory, using the third error detection code read from the first memory.
8. The memory system of claim 1 , wherein the second error detection circuit detects errors of the system data and the first error detection code, which are read from the first memory, and errors of the logical address and the physical address, which are generated through the host address transferred from the host, using the second error detection code read from the first memory.
9. The memory system of claim 1 , wherein the first error detection circuit detects errors of the host data included in the system data read from the first memory and the host address transferred from the host, using the first error detection code read from the first memory.
10. A memory system comprising:
a first error detection circuit configured to generate a first-first error detection code using first host data and a first host address which are transferred from a host and generate a second-first error detection code using second host data and a second host address which are transferred from the host;
a second error detection circuit configured to generate a second error detection code using system data including the first and second host data, a logical address corresponding to the first and second host addresses, a physical address corresponding to the logical address and the first-first and second-first error detection codes;
a third error detection circuit configured to generate a third error detection code using the system data, the first-first and second-first error detection codes and the second error detection code; and
a first memory configured to store the system data, the first-first and second-first error detection codes, the second error detection code and the third error detection code.
11. The memory system of claim 10 , further comprising a second memory configured to store a mapping table between the logical address and the physical address.
12. The memory system of claim 10 , wherein the first error detection circuit generates the first-first error detection code by further using a first poison bit and generated the second-first error detection code by further using a second poison bit,
the second error detection circuit generates the second error detection code by further using the first and second poison bits,
the third error detection circuit generates the third error detection code by further using the first and second poison bits, and
the first memory further stores the first and second poison bits.
13. The memory system of claim 12 , wherein the second error detection circuit generates the second error detection code by further using meta data,
the third error detection circuit generates the third error detection code by further using the meta data, and
the first memory further stores the meta data.
14. The memory system of claim 10 , wherein the third error detection code comprises information for detecting errors of the system data, the first-first and second-first error detection codes and the second error detection code and correcting the detected errors.
15. The memory system of claim 10 , wherein each of the first-first and second-first error detection codes is a cyclic redundancy check (CRC) code,
the second error detection code is a CRC code, and
the third error detection code is a Reed-Solomon (RS) code.
16. The memory system of claim 10 , wherein the third error detection circuit detects errors of the system data, the first-first and second-first detection codes and the second error detection code, which are read from the first memory, using the third error detection code read from the first memory.
17. The memory system of claim 10 , wherein the second error detection circuit detects errors of the system data and the first-first and second-first error detection codes, which are read from the first memory, and errors of the logical address and the physical address, which are generated through the first and second host addresses transferred from the host, using the second error detection code read from the first memory.
18. The memory system of claim 10 , wherein the first error detection circuit detects errors of the first host data read from the first memory and the first host address transferred from the host, using the first-first error detection code read from the first memory and detects errors of the second host data read from the first memory and the second host address transferred from the host, using the second-first error detection code read from the first memory.