Semiconductor device and method of manufacture
A semiconductor device and method of manufacture are provided in which a passivation layer is patterned. In embodiments, by-products from the patterning process are removed using the same etching chamber and at the same time as the removal of a photoresist utilized in the patterning process. Such processes may be used during the manufacturing of FinFET devices.
1. A semiconductor device comprising:
a plurality of metallization layers over a substrate;
a first passivation layer over the plurality of metallization layers;
a first conductive connection, wherein a first portion of the first conductive connection has a first sidewall aligned with a second sidewall of the first passivation layer and a second portion of the first conductive connection being embedded within the first passivation layer;
a capping layer over and in physical contact with the first conductive connection; and
a second passivation layer in physical contact with and extending along both the first sidewall and the second sidewall, wherein a third sidewall of the second passivation layer is aligned with a fourth sidewall of the capping layer, and wherein the second passivation layer extends above the capping layer.
2. The semiconductor device of claim 1 , wherein the second passivation layer is a composite layer.
3. The semiconductor device of claim 2 , wherein the composite layer comprises a first layer, the first layer comprising undoped silicate glass.
4. The semiconductor device of claim 3 , wherein the composite layer comprises a second layer over the first layer, the second layer comprising silicon nitride.
5. The semiconductor device of claim 4 , wherein the first layer has a thickness of between about 2 KÅ and 4 KÅ.
6. The semiconductor device of claim 5 , wherein the second layer has a thickness of between about 2 KÅ and about 6 KÅ.
7. The semiconductor device of claim 1 , wherein the third sidewall is free from carbon-fluorine byproducts.
8. A semiconductor device comprising:
a first conductive connection electrically connected to a metallization layer over a semiconductor substrate;
a first passivation layer over the semiconductor substrate, a first portion of the first passivation layer extending between a second portion of the first conductive connection and the semiconductor substrate in a direction perpendicular to a major surface of the semiconductor substrate;
a capping layer adjacent to a first side of the first conductive connection;
a barrier layer adjacent to a second side of the first conductive connection opposite the first side, wherein the first conductive connection has a first sidewall aligned with a second sidewall of the capping layer, a third sidewall of the barrier layer, and a fourth sidewall of the first passivation layer, and wherein the first conductive connection is coterminous with the capping layer and the barrier layer; and
a first composite layer overlying the capping layer, wherein the first composite layer has a fifth sidewall aligned with a sixth sidewall of the capping layer, the fifth sidewall and the sixth sidewall being free from carbon-fluorine byproducts.
9. The semiconductor device of claim 8 , wherein the first composite layer comprises a first portion, the first portion comprising undoped silicate glass.
10. The semiconductor device of claim 9 , wherein the first composite layer comprises a second portion over the first portion, the second portion comprising silicon nitride.
11. The semiconductor device of claim 10 , wherein the first portion has a first thickness of between about 2 KÅ and about 4 KÅ.
12. The semiconductor device of claim 11 , wherein the second portion has a second thickness of between about 2 KÅ and about 6 KÅ.
13. The semiconductor device of claim 8 , wherein the fifth sidewall faces a first opening, the first opening having a width between about 1 μm and about 10 μm.
14. A semiconductor device comprising:
a plurality of metallization layers over a substrate, the plurality of metallization layers having a top metallization layer;
a structure extending away from the top metallization layer, the structure having a first planar sidewall, the first planar sidewall comprising:
a first material of a first passivation layer;
a second material of a first barrier layer;
a third material of a first conductive contact, wherein a portion of the third material extends at least partially through the first material; and
a fourth material of a capping layer; and
a second passivation layer overlying the first planar sidewall.
15. The semiconductor device of claim 14 , wherein the second passivation layer is a composite layer.
16. The semiconductor device of claim 15 , wherein the composite layer comprises a first portion, the first portion comprising undoped silicate glass.
17. The semiconductor device of claim 16 , wherein the composite layer comprises a second portion over the first portion, the second portion comprising silicon nitride.
18. The semiconductor device of claim 17 , wherein the first portion has a first thickness of between about 2 KÅ and about 4 KÅ.
19. The semiconductor device of claim 18 , wherein the second portion has a second thickness of between about 2 KÅ and about 6 KÅ.
20. The semiconductor device of claim 14 , further comprising an opening through the second passivation layer, the opening having a width between about 1 μm and about 10 μm.