Antifuse OTP structure with hybrid device and hybrid junction for select transistor
An antifuse One-Time-Programmable memory cell includes a substrate, a select transistor formed on the substrate, and an antifuse capacitor formed on the substrate. The select transistor includes a first gate dielectric layer formed on the substrate, a first gate formed on the gate dielectric layer, a first low-voltage junction formed in the substrate, and a second low-voltage junction formed in the substrate. A source and a drain for the select transistor are formed by the first low-voltage junction and the second low-voltage junction. The antifuse capacitor includes a second gate dielectric layer formed on the substrate, a second gate formed on the gate dielectric layer, a third low-voltage junction formed in the substrate, and a fourth low-voltage junction formed in the substrate. A source and a drain for the antifuse capacitor are respectively formed by the third low-voltage junction and the fourth low-voltage junction.
1. An antifuse One-Time-Programmable memory cell, comprising:
a substrate;
one or more transistor-capacitor (1T1C) branches, each comprising:
a first select transistor formed on the substrate, wherein the first select transistor includes:
a first gate dielectric layer formed on the substrate,
a first gate formed on the gate dielectric layer;
a first low-voltage junction formed in the substrate; and
a second low-voltage junction formed in the substrate,
wherein a source and a drain for the first select transistor are formed by the first low-voltage junction and the second low-voltage junction; and
an antifuse capacitor formed on the substrate, wherein the antifuse capacitor includes:
a second gate dielectric layer formed on the substrate,
a second gate formed on the gate dielectric layer;
a third low-voltage junction formed in the substrate; and
a fourth low-voltage junction formed in the substrate,
wherein a source and a drain for the antifuse capacitor are respectively formed by the third low-voltage junction and the fourth low-voltage junction,
wherein the second low-voltage junction and the third low-voltage junction are electrically connected; and
a second select transistor formed on the substrate and in connection with the first select transistor, wherein the second select transistor includes:
a third gate dielectric layer formed on the substrate,
a third gate formed on the gate dielectric layer;
a fifth low-voltage junction formed in the substrate; and
a sixth low-voltage junction formed in the substrate,
wherein a source and a drain for the second select transistor are formed by the fifth low-voltage junction and the sixth low-voltage junction,
wherein the first low-voltage junction and the fifth low-voltage junction are electrically connected,
wherein the third gate dielectric layer has a larger area than the first gate dielectric layer, which reduces high voltage stress in the first select transistor.
2. The antifuse One-Time-Programmable memory cell of claim 1 , further comprising:
two or more transistor-capacitor (1T1C) branches,
wherein the second select transistor is in connection with the first select transistor in each of the two or more transistor-capacitor (1T1C) branches.
3. The antifuse One-Time-Programmable memory cell of claim 2 , wherein the third gate dielectric layer has a larger area than the first gate dielectric layer in the first select transistor in each of the two or more transistor-capacitor (1T1C) branches, which reduces high voltage stress in the first select transistor in each of the two or more transistor-capacitor (1T1C) branches.
4. The antifuse One-Time-Programmable memory cell of claim 1 , wherein the first low-voltage junction or the second low-voltage junction or the third low-voltage junction or the fourth low-voltage junction or the fifth low-voltage junction or the sixth low-voltage junction has a threshold junction breakdown voltage below 3.2 Volt.
5. The antifuse One-Time-Programmable memory cell of claim 4 , wherein the first low-voltage junction or the second low-voltage junction or the third low-voltage junction or the fourth low-voltage junction or the fifth low-voltage junction or the sixth low-voltage junction has a threshold junction breakdown voltage below 2.3 Volt.