Vertical field-effect transistor with T-shaped gate
A method of forming a semiconductor structure includes forming a fin over a substrate, forming a bottom source/drain over the substrate surrounding a first portion of sidewalls of the fin, and forming a bottom spacer over the bottom source/drain and surrounding a second portion of the sidewalls of the fin. The method also includes forming a T-shaped gate stack over the bottom spacer and surrounding a third portion of the sidewalls of the fin, forming a top spacer over the T-shaped gate stack and surrounding a fourth portion of the sidewalls of the fin, and forming a top source/drain over the top spacer and surrounding a fifth portion of the sidewalls and a top surface of the fin. The T-shaped gate stack includes a gate dielectric, a gate conductor, and a gate metal extending outward from a portion of sidewalls of the gate conductor between the bottom and top spacers.
1. An integrated circuit comprising:
a vertical field-effect transistor structure comprising:
a substrate;
at least one fin disposed over the substrate, the at least one fin providing a channel for at least one vertical field-effect transistor;
a bottom source/drain region disposed over the substrate surrounding a first portion of sidewalls of the at least one fin;
a bottom spacer disposed over the bottom source/drain region and surrounding a second portion of the sidewalls of the at least one fin;
a T-shaped gate stack disposed over the bottom spacer and surrounding a third portion of the sidewalls of the at least one fin;
a top spacer disposed over the T-shaped gate stack and surrounding a fourth portion of the sidewalls of the at least one fin; and
a top source/drain region disposed over the top spacer and surrounding a fifth portion of the sidewalls and a top surface of the at least one fin;
wherein the T-shaped gate stack comprises a gate dielectric layer surrounding the third portion of the sidewalls of the at least one fin, a gate conductor layer surrounding the gate dielectric layer, and a gate metal layer extending outward from a portion of sidewalls of the gate conductor layer between the bottom spacer and the top spacer.
2. A semiconductor structure comprising:
a substrate;
at least one fin disposed over the substrate, the at least one fin providing a channel for at least one vertical field-effect transistor;
a bottom source/drain region disposed over the substrate surrounding a first portion of sidewalls of the at least one fin;
a bottom spacer disposed over the bottom source/drain region and surrounding a second portion of the sidewalls of the at least one fin;
a T-shaped gate stack disposed over the bottom spacer and surrounding a third portion of the sidewalls of the at least one fin;
a top spacer disposed over the T-shaped gate stack and surrounding a fourth portion of the sidewalls of the at least one fin; and
a top source/drain region disposed over the top spacer and surrounding a fifth portion of the sidewalls and a top surface of the at least one fin;
wherein the T-shaped gate stack comprises a gate dielectric layer surrounding the third portion of the sidewalls of the at least one fin, a gate conductor layer surrounding the gate dielectric layer, and a gate metal layer extending outward from a portion of sidewalls of the gate conductor layer between the bottom spacer and the top spacer.
3. The semiconductor structure of claim 2 , wherein a thickness of the bottom spacer below the gate metal layer is greater than a thickness of the top spacer above the gate metal layer.
4. The semiconductor structure of claim 2 , wherein the bottom spacer comprises:
a first portion disposed over a top surface of the bottom source/drain region surrounding the second portion of the sidewalls of the at least one fin; and
a second portion disposed over a top surface of the first portion of the bottom spacer and surrounding a portion of the sidewalls of the gate conductor layer.
5. The semiconductor structure of claim 4 , wherein the top spacer comprises:
a first portion disposed over a top surface of the gate metal layer and surrounding a remaining portion of the sidewalls of the gate conductor layer; and
a second portion disposed over a top surface of the first portion of the top spacer, a top surface of the gate dielectric layer, a top surface of the gate conductor layer, and surrounding the fourth portion of the sidewalls of the at least one fin.
6. The semiconductor structure of claim 5 , further comprising an interlayer dielectric layer disposed over a remaining portion of the top surface of the second portion of the bottom spacer, a top surface of the second portion of the top spacer, and the top source/drain region.
7. The semiconductor structure of claim 6 , further comprising:
a gate contact disposed in a first trench in the interlayer dielectric layer, the first trench extending from a top surface of the interlayer dielectric layer to a portion of the top surface of the gate metal layer spaced apart from a first sidewall of the at least one fin;
a top/source drain contact disposed in a second trench in the interlayer dielectric layer, the second trench extending from the top surface of the interlayer dielectric layer to a portion of a top surface of the top source/drain region; and
a bottom source/drain contact disposed in a third trench in the interlayer dielectric layer, the third trench extending from the top surface of the interlayer dielectric layer to a portion of a top surface of the bottom source/drain region.