Image encoding device, image decoding device, image encoding method, and image decoding method
The present disclosure provides systems and methods for video coding. The systems include, for example, an image encoder comprising: circuitry; and a memory coupled to the circuitry, wherein the circuitry, in operation, performs the following: predicting a first block of prediction samples for a current block of a picture, wherein predicting the first block of prediction samples includes at least a prediction process with a motion vector from a different picture; padding the first block of prediction samples to form a second block of prediction samples, wherein the second block is larger than the first block; calculating at least a gradient using the second block of prediction samples; and encoding the current block using at least the calculated gradient.
1. An image encoder comprising:
circuitry; and
a memory coupled to the circuitry,
wherein the circuitry, in operation, performs the following:
predicting a first block of prediction samples for a current block of a picture, wherein predicting the first block of prediction samples includes at least a prediction process with a motion vector from a different picture;
padding the first block of prediction samples to form a second block of prediction samples, wherein the second block is larger than the first block;
calculating at least a gradient using the second block of prediction samples; and
encoding the current block using at least the calculated gradient,
wherein the circuitry performs the following when padding the first block of prediction samples to form the second block of prediction samples:
duplicating sample values of prediction samples located inside of the first block and along each edge of the first block to generate corresponding sample values of prediction samples located inside of the second block and outside of the first block, and
wherein the corresponding sample values of prediction samples located inside of the second block and outside the first block surround the first block so as to be respectively adjacent to the sample values of prediction samples located inside of the first block and along each edge of the first block.
2. The image encoder of claim 1 , wherein the circuitry further performs the following when predicting the first block of prediction samples for the current block of the picture:
predicting another block of prediction samples for the current block of the picture, wherein predicting the other block of prediction samples includes at least a prediction process with another motion vector from another different picture.
3. The image encoder of claim 2 , wherein the circuitry further performs the following when padding the first block of prediction samples to form the second block of prediction samples:
padding the other block of prediction samples to form yet another block of prediction samples.
4. The image encoder of claim 1 , wherein the circuitry performs an interpolation process for a prediction mode before or after the circuitry pads the first block of prediction samples to form the second block of prediction samples, wherein the prediction mode is a merge mode or an inter prediction mode, and
wherein when encoding the current block using at least the calculated gradient, the circuitry encodes the current block using a resulting block of prediction samples produced by the interpolation process and at least the calculated gradient.
5. An image encoder comprising:
circuitry; and
a memory coupled to the circuitry,
wherein the circuitry, in operation, performs the following:
predicting a first block of prediction samples for a current block of a picture, wherein predicting the first block of prediction samples includes at least a prediction process with a motion vector from a different picture;
padding the first block of prediction samples to form a second block of prediction samples, wherein the second block is larger than the first block;
performing an interpolation process using the second block of prediction samples; and
encoding the current block using at least a resulting block of the interpolation process,
wherein the circuitry performs the following when padding the first block of prediction samples to form the second block of prediction samples:
duplicating sample values of prediction samples located inside of the first block and along each edge of the first block to generate corresponding sample values of prediction samples located inside of the second block and outside of the first block, and
wherein the corresponding sample values of prediction samples located inside of the second block and outside the first block surround the first block so as to be respectively adjacent to the sample values of prediction samples located inside of the first block and along each edge of the first block.
6. The image encoder according to claim 5 , wherein the circuitry, in operation, performs the following:
performing an overlapped block motion compensation process for predicting one or more neighboring blocks of the current block, wherein the overlapped block motion compensation process uses at least a resulting block of the interpolation process.
7. An image decoder comprising:
circuitry;
a memory coupled to the circuitry,
wherein the circuitry, in operation, performs the following:
predicting a first block of prediction samples for a current block of a picture, wherein predicting the first block of prediction samples includes at least a prediction process with a motion vector from a different picture;
padding the first block of prediction samples to form a second block of prediction samples, wherein the second block is larger than the first block;
calculating at least a gradient using the second block of prediction samples; and
decoding the current block using at least the calculated gradient,
wherein the circuitry performs the following when padding the first block of prediction samples to form the second block of prediction samples:
duplicating sample values of prediction samples located inside of the first block and along each edge of the first block to generate corresponding sample values of prediction samples located inside of the second block and outside of the first block, and
wherein the corresponding sample values of prediction samples located inside of the second block and outside the first block surround the first block so as to be respectively adjacent to the sample values of prediction samples located inside of the first block and along each edge of the first block.
8. The image decoder of claim 7 , wherein the circuitry further performs the following when predicting the first block of prediction samples for the current block of the picture:
predicting another block of prediction samples for the current block of the picture, wherein predicting the other block of prediction samples includes at least a prediction process with another motion vector from another different picture.
9. The image decoder of claim 8 , wherein the circuitry further performs the following when padding the first block of prediction samples to form the second block of prediction samples:
padding the other block of prediction samples to form yet another block of prediction samples.
10. The image decoder of claim 9 , wherein the circuitry performs an interpolation process for a prediction mode before or after the circuitry pads the first block of prediction samples to form the second block of prediction samples, wherein the prediction mode is a merge mode or an inter prediction mode, and
wherein when decoding the current block using at least the calculated gradient, the circuitry decodes the current block using a resulting block of prediction samples produced by the interpolation process and at least the calculated gradient.
11. An image decoder comprising:
circuitry; and
a memory coupled to the circuitry,
wherein the circuitry, in operation, performs the following:
predicting a first block of prediction samples for a current block of a picture, wherein predicting the first block of prediction samples includes at least a prediction process with a motion vector from a different picture;
padding the first block of prediction samples to form a second block of prediction samples, wherein the second block is larger than the first block;
performing an interpolation process using the second block of prediction samples; and
decoding the current block using at least a resulting block of the interpolation process,
wherein the circuitry performs the following when padding the first block of prediction samples to form the second block of prediction samples:
duplicating sample values of prediction samples located inside of the first block and along each edge of the first block to generate corresponding sample values of prediction samples located inside of the second block and outside of the first block, and
wherein the corresponding sample values of prediction samples located inside of the second block and outside the first block surround the first block so as to be respectively adjacent to the sample values of prediction samples located inside of the first block and along each edge of the first block.
12. The image decoder of claim 11 , wherein the circuitry, in operation, performs the following:
performing an overlapped block motion compensation process for predicting one or more neighboring blocks of the current block, wherein the overlapped block motion compensation process uses at least a resulting block of the interpolation process.