In-memory computation device
An in-memory computation device including a memory array, p×q analog to digital converters (ADCs) and a ladder adder is provided. The memory array is divided into p×q memory tiles, where p and q are positive integers larger than 1. Each of the memory tiles has a plurality local bit lines coupled to a global bit line respectively through a plurality of bit line selection switches. The bit line selection switches are turned on or cur off according to a plurality of control signals. The memory array receives a plurality of input signals. The ADCs are respectively coupled to a plurality of global bit lines of the memory tiles. The ADCs respectively convert electrical signals on the global bit lines to generate a plurality of sub-output signals. The ladder adder is coupled to the ADCs, and performs an addition operation on the sub-output signals to generate a calculation result.
1. An in-memory computation device, comprising:
a memory array, divided into p×q memory tiles, wherein p and q are positive integers larger than 1, and the memory array receives a plurality of input signals, each memory tile is respectively coupled to one of a plurality of global bit lines, where each of the memory tiles has a plurality of local bit lines coupled to a corresponding global bit line through a plurality of bit line selection switches, and the bit line selection switches are respectively controlled by a plurality of control signals to be turned on or cut off;
p×q analog-to-digital converters, respectively coupled to the global bit lines of the memory tiles, and respectively converting electrical signals on the global bit lines to generate p×q digital sub-output signals; and
a ladder adder, coupled to the analog-to-digital converters, and performing an addition operation on the sub-output signals to generate a calculation result.
2. The in-memory computation device as claimed in claim 1 , wherein a turn on number of the bit line selection switches of each of the memory tiles represents a bit number of a weight.
3. The in-memory computation device as claimed in claim 1 , wherein the ladder adder comprises:
p first sub-ladder adders, each of the first sub-ladder adders being respectively coupled to q of the analog-to-digital converters, and the first sub-ladder adders respectively generating p first direction calculation results; and
a second sub-ladder adder, coupled to the first sub-ladder adders, and generating the calculation result according to the first direction calculation results.
4. The in-memory computation device as claimed in claim 3 , wherein each of the first sub-ladder adders has N layers, and each layer comprises at least one full adder and at least one bit shifter, wherein N=log 2 q.
5. The in-memory computation device as claimed in claim 4 , wherein a first layer of each of the first sub-ladder adders has q/2 of the at least one full adder and q/2 of the at least one bit shifter, and the at least one full adder and the at least one bit shifter are sequentially arranged in interleaving to respectively receive the corresponding sub-output signals.
6. The in-memory computation device as claimed in claim 5 , wherein a r th layer of each of the first sub-ladder adders has q/2 r of the at least one full adder and q/2 r of the at least one bit shifter, and the at least one full adder and the at least one bit shifter in the same layer are sequentially arranged in interleaving, and are respectively coupled to an output terminal of the at least one full adder of a previous layer, wherein 1<r≤N.
7. The in-memory computation device as claimed in claim 3 , wherein the second sub-ladder adder has M layers, and each layer comprises at least one full adder and at least one bit shifter, wherein M=log 2 p , and the at least one full adder and the at least one bit shifter are arranged in interleaving to respectively receive the first direction calculation results.
8. The in-memory computation device as claimed in claim 7 , wherein a first layer of the second sub-ladder adder has p/2 of the at least one full adder and p/2 of the at least one bit shifter, and the at least one full adder and the at least one bit shifter are sequentially arranged in interleaving to respectively receive the first direction calculation results.
9. The in-memory computation device as claimed in claim 7 , wherein an s th layer of the second sub-ladder adder has p/2 s of the at least one full adder and p/2 s of the at least one bit shifter, and the at least one full adder and the at least one bit shifter in the same layer are sequentially arranged in interleaving, and are respectively coupled to an output terminal of the at least one full adder of a previous layer, wherein 1<s≤M.
10. The in-memory computation device as claimed in claim 1 , further comprising:
a normalization circuit, coupled to the ladder adder, and performing a normalization operation on the calculation result according to a scaling factor and a bias factor to generate an adjusted calculation result.
11. The in-memory computation device as claimed in claim 10 , further comprising:
a quantizer, coupled to the normalization circuit, and performing a quantization operation on the adjusted calculation result according to a reference value to generate an output calculation result.
12. The in-memory computation device as claimed in claim 11 , wherein the quantizer is a divider, and the divider divides the adjusted calculation result by the reference value to generate the output calculation result.
13. The in-memory computation device as claimed in claim 10 , wherein the normalization circuit comprises:
a multiplier, multiplying the calculation result and the scaling factor; and
a full adder, adding an output of the multiplier and the bias factor to generate the adjusted calculation result.
14. The in-memory computation device as claimed in claim 1 , wherein the memory array comprises a plurality of 2T NOR flash memory cells.
15. The in-memory computation device as claimed in claim 1 , wherein a control terminal of a selection transistor corresponding to each of the 2T NOR flash memory cell receives one of the input signals.