Microcontroller, memory system having the same, and method for operating the same

1. A memory system comprising:

a semiconductor memory device performing a scanning operation on ROM data stored in a microcontroller in a test operation and outputting a result of the scanning operation as a status output signal; and

a controller configured to determine whether an error exists in the ROM data, using the status output signal,

wherein the microcontroller includes:

a ROM data divider configured to divide and store the ROM data with a set data size, and sequentially output the stored divided data as main data and sub-data.

2. The memory system of claim 1 , wherein the scanning operation checks whether an error exists in the ROM data to detect the error, using a cyclic redundancy check (CRC) method.

3. The memory system of claim 1 , wherein the microcontroller further includes:

a control logic configured to store the ROM data, output control signals for controlling a peripheral circuit in response to a command input from the outside, and read and output the ROM data in response to a test mode enable signal in the test operation;

a ROM data scanner configured to output a ROM data scanning signal by performing the scanning operation on the main data or the sub-data in response to a scan clock; and

an output circuit configured to poll the ROM data scanning signal in an internal status output signal and output the polled signal as the status output signal.

4. The memory system of claim 3 , wherein the microcontroller further includes:

a test mode enabler configured to generate the test mode enable signal for enabling a test mode after a power-on reset operation, after a reset operation of the microcontroller, or when the test operation is requested from a host; and

a clock period controller configured to generate the scan clock by controlling a micro clock with a set period.

5. The memory system of claim 3 , wherein the control logic includes a main microcontroller and a sub-microcontroller.

6. The memory system of claim 5 , wherein the ROM data divider includes:

a main ROM data divider configured to receive the ROM data stored in the main microcontroller in the test operation, and divide and store the received ROM data according to a set data division size; and

a sub-ROM data divider configured to receive sub-ROM data stored in the sub-microcontroller in the test operation, and divide and store the received sub-ROM data according to the set data division size.

7. The memory system of claim 6 , wherein the main ROM data divider includes a plurality of registers,

wherein the ROM data respectively divided and stored in the plurality of registers are sequentially selected in response to a scan state signal and are output as the main data.

8. The memory system of claim 6 , wherein the sub-ROM data divider includes a plurality of registers,

wherein the sub-ROM data respectively divided and stored in the plurality of registers are sequentially selected in response to a scan state signal and are output as the sub-data.

9. The memory system of claim 3 , wherein the ROM data scanner performs the scanning operation, using a CRC 32 code.