Method for fabricating embedded nanostructures with arbitrary shape
A layered heterostructure, comprising alternating layers of different semiconductors, wherein one of the atom species of one of the semiconductors has a faster diffusion rate along an oxidizing interface than an atom species of the other semiconductor at an oxidizing temperature, can be used to fabricate embedded nanostructures with arbitrary shape. The result of the oxidation will be an embedded nanostructure comprising the semiconductor having slower diffusing atom species surrounded by the semiconductor having the higher diffusing atom species. The method enables the fabrication of low- and multi-dimensional quantum-scale embedded nanostructures, such as quantum dots (QDs), toroids, and ellipsoids.
1. A method for fabricating embedded nanostructures, comprising:
providing a layered heterostructure, comprising alternating layers of at least two different semiconductors, wherein an atom species of one of the semiconductors has a faster diffusion rate along an oxidizing interface than a slower diffusing atom species of the other semiconductor at an oxidizing temperature;
patterning the layered heterostructure to form a patterned heterostructure;
removing portions of the patterned heterostructure to form a vertical heterostructure of arbitrary cross section; and
oxidizing the vertical heterostructure at the oxidizing temperature to form embedded nanostructures having an arbitrary shape of the semiconductor having the slower diffusing atom species surrounded by the semiconductor having the faster diffusing atom species.
2. The method of claim 1 , wherein the layered heterostructure comprises Si/SiGe.
3. The method of claim 2 , wherein the layered heterostructure comprises at least one Si layer between SiGe layers.
4. The method of claim 2 , wherein the embedded nanostructure comprises a embedded Si nanostructure surrounded by a SiGe.
5. The method of claim 4 , wherein the embedded nanostructure comprises a Ge-rich cladding surrounding the embedded Si nanostructure.
6. The method of claim 4 , further comprising implanting the surrounding SiGe with Si ions to amorphize the SiGe.
7. The method of claim 1 , wherein the oxidizing comprises exposing the vertical pillars to O 2 at an oxidizing temperature greater than 800° C.
8. The method of claim 1 , further comprising annealing the embedded nanostructures at an annealing temperature to at least partially remove the surrounding semiconductor.
9. The method of claim 8 , wherein the annealing comprises exposing the embedded nanostructures to O 2 at an annealing temperature of greater than 500° C. and less than 800° C.
10. The method of claim 1 , wherein the embedded nanostructure comprises an L, toroid, dot, or ellipsoid.
11. The method of claim 1 , wherein the embedded nanostructure has a cross-sectional dimension of less than 10 nm.