Gate all around transistors with high charge mobility channel materials
A semiconductor device comprising an N-type metal oxide semiconductor (NMOS) gate-all-around (GAA) transistor and a P-type metal oxide semiconductor (PMOS) GAA transistor with high charge mobility channel materials is disclosed. The semiconductor device may include a substrate. The semiconductor device may also include an NMOS GAA transistor on the substrate, wherein the NMOS GAA transistor comprises a first channel material. The semiconductor device may further include a PMOS GAA transistor on the substrate, wherein the PMOS GAA transistor comprises a second channel material. The first channel material may have an electron mobility greater than an electron mobility of Silicon (Si) and the second channel material may have a hole mobility greater than a hole mobility of Si.
1. A semiconductor device, comprising:
a substrate;
an etch stop layer on the substrate;
an isolation layer on top of the etch stop layer;
an N-type metal oxide semiconductor (NMOS) gate-all-around (GAA) transistor directly on the etch stop layer, the NMOS GAA transistor comprising a first channel material; and
a P-type metal oxide semiconductor (PMOS) GAA transistor directly on the isolation layer, the PMOS GAA transistor comprising a second channel material,
wherein the first channel material has an electron mobility greater than an electron mobility of Silicon (Si) and the second channel material has a hole mobility greater than a hole mobility of Si.
2. The semiconductor device of claim 1 , wherein the substrate comprises at least one of Germanium (Ge), Gallium Arsenide (GaAs), Ge/Si, and GaAs/Si.
3. The semiconductor device of claim 1 , wherein the NMOS GAA transistor comprises a plurality of gate layers and a plurality of channel layers that alternate with one another, and wherein the plurality of channel layers comprise the first channel material.
4. The semiconductor device of claim 3 , wherein the plurality of gate layers comprise Hafnium Oxide (HfO 2 ) and Titanium Aluminum Nitride (TiAlN).
5. The semiconductor device of claim 3 , wherein the first channel material comprises GaAs.
6. The semiconductor device of claim 1 , wherein the PMOS GAA transistor comprises a plurality of gate layers and a plurality of channel layers that alternate with one another, and wherein the plurality of channel layers comprise the second channel material.
7. The semiconductor device of claim 6 , wherein the plurality of gate layers comprise HfO 2 and Titanium Nitride (TiN).
8. The semiconductor device of claim 6 , wherein the second channel material comprises Ge.
9. The semiconductor device of claim 1 , wherein the etch stop layer comprises at least one of GaAs and Aluminum Arsenide (AlAs).
10. The semiconductor device of claim 1 , wherein the isolation layer comprises N-type doped Ge.
11. The semiconductor device of claim 1 , further comprising an isolation structure between the NMOS GAA transistor and the PMOS GAA transistor.
12. The semiconductor device of claim 11 , wherein the isolation structure comprises a shallow trench isolation (STI) region.
13. A method for fabricating a semiconductor device, comprising:
forming an etch stop layer on a substrate;
forming an isolation layer on top of the etch stop layer;
forming an N-type metal oxide semiconductor (NMOS) gate-all-around (GAA) transistor directly on the etch stop layer, the NMOS GAA transistor comprising a first channel material; and
forming a P-type metal oxide semiconductor (PMOS) GAA transistor directly on the isolation layer, the PMOS GAA transistor comprising a second channel material,
wherein the first channel material has an electron mobility greater than an electron mobility of Silicon (Si) and the second channel material has a hole mobility greater than a hole mobility of Si.
14. The method of claim 13 , wherein the NMOS GAA transistor comprises a plurality of gate layers and a plurality of channel layers that alternate with one another, and wherein the plurality of channel layers comprise the first channel material.
15. The method of claim 14 , wherein the first channel material comprises Gallium Arsenide (GaAs).
16. The method of claim 14 , wherein the PMOS GAA transistor comprises a plurality of gate layers and a plurality of channel layers that alternate with one another, and wherein the plurality of channel layers comprise the second channel material.
17. The method of claim 16 , wherein the second channel material comprises Germanium (Ge).
18. The method of claim 14 , wherein the substrate comprises at least one of Ge, GaAs, Ge/Si, and GaAs/Si.